diff options
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Attach.scala | 2 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 8 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Binding.scala | 8 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 2 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala | 4 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/RawModule.scala (renamed from chiselFrontend/src/main/scala/chisel3/core/UserModule.scala) | 13 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 6 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
8 files changed, 24 insertions, 21 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala index b3096fd5..8cb58f1c 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala @@ -14,7 +14,7 @@ object attach { // scalastyle:ignore object.name AttachException(": Conditional attach is not allowed!") // Actual implementation - private[core] def impl(elts: Seq[Analog], contextModule: UserModule)(implicit sourceInfo: SourceInfo): Unit = { + private[core] def impl(elts: Seq[Analog], contextModule: RawModule)(implicit sourceInfo: SourceInfo): Unit = { if (Builder.whenDepth != 0) throw ConditionalAttachException // TODO Check that references are valid and can be attached diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala index ad7ba98a..897ccacf 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -55,7 +55,7 @@ object BiConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: UserModule): Unit = { + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { (left, right) match { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => @@ -154,7 +154,7 @@ object BiConnect { connectCompileOptions: CompileOptions, left_r: Record, right_r: Record, - context_mod: UserModule): Unit = { + context_mod: RawModule): Unit = { // Verify right has no extra fields that left doesn't have for((field, right_sub) <- right_r.elements) { if(!left_r.elements.isDefinedAt(field)) { @@ -207,7 +207,7 @@ object BiConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: UserModule): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If left or right have no location, assume in context module // This can occur if one of them is a literal, unbound will error previously @@ -313,7 +313,7 @@ object BiConnect { // This function checks if analog element-level attaching is allowed // Then it either issues it or throws the appropriate exception. - def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: UserModule): Unit = { + def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: RawModule): Unit = { // Error if left or right is BICONNECTED in the current module already for (elt <- left :: right :: Nil) { elt.biConnectLocs.get(contextModule) match { diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala index 60235477..4c352bc6 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala @@ -96,11 +96,11 @@ sealed trait ReadOnlyBinding extends TopBinding // TODO(twigg): Ops between unenclosed nodes can also be unenclosed // However, Chisel currently binds all op results to a module -case class OpBinding(enclosure: UserModule) extends ConstrainedBinding with ReadOnlyBinding -case class MemoryPortBinding(enclosure: UserModule) extends ConstrainedBinding +case class OpBinding(enclosure: RawModule) extends ConstrainedBinding with ReadOnlyBinding +case class MemoryPortBinding(enclosure: RawModule) extends ConstrainedBinding case class PortBinding(enclosure: BaseModule) extends ConstrainedBinding -case class RegBinding(enclosure: UserModule) extends ConstrainedBinding -case class WireBinding(enclosure: UserModule) extends ConstrainedBinding +case class RegBinding(enclosure: RawModule) extends ConstrainedBinding +case class WireBinding(enclosure: RawModule) extends ConstrainedBinding case class ChildBinding(parent: Data) extends Binding { def location = parent.topBinding.location diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index abc7b583..83c8637a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -1734,7 +1734,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element { // Used to enforce single bulk connect of Analog types, multi-attach is still okay // Note that this really means 1 bulk connect per Module because a port can // be connected in the parent module as well - private[core] val biConnectLocs = mutable.Map.empty[UserModule, SourceInfo] + private[core] val biConnectLocs = mutable.Map.empty[RawModule, SourceInfo] // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala index d4c80405..0773c7a2 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala @@ -64,7 +64,7 @@ object MonoConnect { connectCompileOptions: CompileOptions, sink: Data, source: Data, - context_mod: UserModule): Unit = + context_mod: RawModule): Unit = (sink, source) match { // Handle legal element cases, note (Bool, Bool) is caught by the first two, as Bool is a UInt @@ -157,7 +157,7 @@ object MonoConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: UserModule): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If source has no location, assume in context module // This can occur if is a literal, unbound will error previously diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala index 5183f860..1a9911e6 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala @@ -13,8 +13,10 @@ import chisel3.internal.firrtl.{Command => _, _} import chisel3.internal.sourceinfo.UnlocatableSourceInfo /** Abstract base class for Modules that contain Chisel RTL. + * This abstract base class is a user-defined module which does not include implicit clock and reset and supports + * multiple IO() declarations. */ -abstract class UserModule(implicit moduleCompileOptions: CompileOptions) +abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends BaseModule { // // RTL construction internals @@ -58,7 +60,7 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions) require(!_closed, "Can't generate module more than once") _closed = true - val names = nameIds(classOf[UserModule]) + val names = nameIds(classOf[RawModule]) // Ports get first naming priority, since they are part of a Module's IO spec namePorts(names) @@ -114,11 +116,12 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions) /** Abstract base class for Modules, which behave much like Verilog modules. * These may contain both logic and state which are written in the Module * body (constructor). + * This abstract base class includes an implicit clock and reset. * * @note Module instantiations must be wrapped in a Module() call. */ -abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions) - extends UserModule { +abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions) + extends RawModule { // Implicit clock and reset pins val clock: Clock = IO(Input(Clock())) val reset: Reset = IO(Input(Bool())) @@ -143,7 +146,7 @@ abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions) * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins. */ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) - extends ImplicitModule { + extends MultiIOModule { // These are to be phased out protected var override_clock: Option[Clock] = None protected var override_reset: Option[Bool] = None diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 0938ea9e..f0bb5605 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -222,8 +222,8 @@ private[chisel3] object Builder { // A bare api call is, e.g. calling Wire() from the scala console). ) } - def forcedUserModule: UserModule = currentModule match { - case Some(module: UserModule) => module + def forcedUserModule: RawModule = currentModule match { + case Some(module: RawModule) => module case _ => throwException( "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // A bare api call is, e.g. calling Wire() from the scala console). @@ -325,7 +325,7 @@ private[chisel3] object Builder { throwException(m) } - def build[T <: UserModule](f: => T): Circuit = { + def build[T <: RawModule](f: => T): Circuit = { chiselContext.withValue(new ChiselContext) { dynamicContextVar.withValue(Some(new DynamicContext())) { errors.info("Elaborating design...") diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index ae8b248a..c05d402d 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -286,7 +286,7 @@ abstract class Component extends Arg { def name: String def ports: Seq[Port] } -case class DefModule(id: UserModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation] = Seq.empty) |