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-rw-r--r--chiselFrontend/src/main/scala/chisel3/Aggregate.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
index ba9afd5b..eaa56c36 100644
--- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
@@ -65,7 +65,7 @@ sealed abstract class Aggregate extends Data {
private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
compileOptions: CompileOptions): Unit = {
var i = 0
- val bits = WireDefault(UInt(this.width), that) // handles width padding
+ val bits = if (that.isLit) that else WireDefault(UInt(this.width), that) // handles width padding
for (x <- flatten) {
val fieldWidth = x.getWidth
if (fieldWidth > 0) {