diff options
Diffstat (limited to 'chiselFrontend')
6 files changed, 68 insertions, 21 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index f2d9558d..a9f89cbc 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -5,6 +5,7 @@ package chisel3.core import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{ModuleIO, DefInvalid} import chisel3.internal.sourceinfo.SourceInfo +import chisel3.NotStrict.NotStrictCompileOptions /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index b4659a52..47003df0 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -9,6 +9,7 @@ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ import chisel3.internal.firrtl.{Command => _, _} import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo} +import chisel3.NotStrict.NotStrictCompileOptions object Module { /** A wrapper method that all Module instantiations must be wrapped in @@ -49,6 +50,7 @@ object Module { */ abstract class Module( override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) + (implicit moduleCompileOptions: ExplicitCompileOptions) extends HasId { // _clock and _reset can be clock and reset in these 2ary constructors // once chisel2 compatibility issues are resolved @@ -186,4 +188,5 @@ extends HasId { } // For debuggers/testers lazy val getPorts = computePorts + val compileOptions = moduleCompileOptions } diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 9f2b1631..9b656dea 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -97,16 +97,16 @@ private[chisel3] trait HasId { private[chisel3] def getRef: Arg = _ref.get } -private[chisel3] class DynamicContext(optionMap: Option[Map[String, String]] = None) { +private[chisel3] class DynamicContext(moduleCompileOptions: Option[ExplicitCompileOptions] = None) { val idGen = new IdGen val globalNamespace = new Namespace(None, Set()) val components = ArrayBuffer[Component]() var currentModule: Option[Module] = None val errors = new ErrorLog - val compileOptions = new CompileOptions(optionMap match { - case Some(map: Map[String, String]) => map - case None => Map[String, String]() - }) + val compileOptions = moduleCompileOptions match { + case Some(options: ExplicitCompileOptions) => options + case None => chisel3.NotStrict.NotStrictCompileOptions + } } private[chisel3] object Builder { @@ -147,8 +147,8 @@ private[chisel3] object Builder { def errors: ErrorLog = dynamicContext.errors def error(m: => String): Unit = errors.error(m) - def build[T <: Module](f: => T, optionMap: Option[Map[String, String]] = None): Circuit = { - dynamicContextVar.withValue(Some(new DynamicContext(optionMap))) { + def build[T <: Module](f: => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): Circuit = { + dynamicContextVar.withValue(Some(new DynamicContext(moduleCompileOptions))) { errors.info("Elaborating design...") val mod = f mod.forceName(mod.name, globalNamespace) diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala index 31d441c1..2890f6dc 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala @@ -2,21 +2,32 @@ package chisel3.internal -/** Initialize compilation options from a string map. - * - * @param optionsMap the map from "option" to "value" - */ -class CompileOptions(optionsMap: Map[String, String]) { - // The default for settings related to "strictness". - val strictDefault: String = optionsMap.getOrElse("strict", "false") - val looseDefault: String = (!(strictDefault.toBoolean)).toString +trait CompileOptions { // Should Bundle connections require a strict match of fields. // If true and the same fields aren't present in both source and sink, a MissingFieldException, // MissingLeftFieldException, or MissingRightFieldException will be thrown. - val connectFieldsMustMatch: Boolean = optionsMap.getOrElse("connectFieldsMustMatch", strictDefault).toBoolean - val regTypeMustBeUnbound: Boolean = optionsMap.getOrElse("regTypeMustBeUnbound", strictDefault).toBoolean - val declaredTypeMustBeUnbound: Boolean = optionsMap.getOrElse("declaredTypeMustBeUnbound", strictDefault).toBoolean - val requireIOWrap: Boolean = optionsMap.getOrElse("requireIOWrap", strictDefault).toBoolean - val dontTryConnectionsSwapped: Boolean = optionsMap.getOrElse("dontTryConnectionsSwapped", strictDefault).toBoolean - val dontAssumeDirectionality: Boolean = optionsMap.getOrElse("dontAssumeDirectionality", strictDefault).toBoolean + val connectFieldsMustMatch: Boolean + val declaredTypeMustBeUnbound: Boolean + val requireIOWrap: Boolean + val dontTryConnectionsSwapped: Boolean + val dontAssumeDirectionality: Boolean } + +trait ExplicitCompileOptions extends CompileOptions + +///** Initialize compilation options from a string map. +// * +// * @param optionsMap the map from "option" to "value" +// */ +//class CompileOptions(optionsMap: Map[String, String]) { +// // The default for settings related to "strictness". +// val strictDefault: String = optionsMap.getOrElse("strict", "false") +// // Should Bundle connections require a strict match of fields. +// // If true and the same fields aren't present in both source and sink, a MissingFieldException, +// // MissingLeftFieldException, or MissingRightFieldException will be thrown. +// val connectFieldsMustMatch: Boolean = optionsMap.getOrElse("connectFieldsMustMatch", strictDefault).toBoolean +// val declaredTypeMustBeUnbound: Boolean = optionsMap.getOrElse("declaredTypeMustBeUnbound", strictDefault).toBoolean +// val requireIOWrap: Boolean = optionsMap.getOrElse("requireIOWrap", strictDefault).toBoolean +// val dontTryConnectionsSwapped: Boolean = optionsMap.getOrElse("dontTryConnectionsSwapped", strictDefault).toBoolean +// val dontAssumeDirectionality: Boolean = optionsMap.getOrElse("dontAssumeDirectionality", strictDefault).toBoolean +//} diff --git a/chiselFrontend/src/main/scala/chisel3/notstrict.scala b/chiselFrontend/src/main/scala/chisel3/notstrict.scala new file mode 100644 index 00000000..dc4bf807 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/notstrict.scala @@ -0,0 +1,16 @@ +// See LICENSE for license details. + +package chisel3 + +import chisel3.internal.ExplicitCompileOptions + + +object NotStrict { + implicit object NotStrictCompileOptions extends ExplicitCompileOptions { + val connectFieldsMustMatch = false + val declaredTypeMustBeUnbound = false + val requireIOWrap = false + val dontTryConnectionsSwapped = false + val dontAssumeDirectionality = false + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/strict.scala b/chiselFrontend/src/main/scala/chisel3/strict.scala new file mode 100644 index 00000000..f6db8765 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/strict.scala @@ -0,0 +1,16 @@ +// See LICENSE for license details. + +package chisel3 + +import chisel3.internal.ExplicitCompileOptions + + +object Strict { + implicit object StrictCompileOptions extends ExplicitCompileOptions { + val connectFieldsMustMatch = true + val declaredTypeMustBeUnbound = true + val requireIOWrap = true + val dontTryConnectionsSwapped = true + val dontAssumeDirectionality = true + } +} |