diff options
Diffstat (limited to 'chiselFrontend')
3 files changed, 26 insertions, 7 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Mem.scala b/chiselFrontend/src/main/scala/chisel3/Mem.scala index 7fbbaefd..24ab4b8e 100644 --- a/chiselFrontend/src/main/scala/chisel3/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/Mem.scala @@ -4,11 +4,14 @@ package chisel3 import scala.language.experimental.macros +import firrtl.{ir => fir} + import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform, UnlocatableSourceInfo, MemTransform} + object Mem { /** Creates a combinational/asynchronous-read, sequential/synchronous-write [[Mem]]. @@ -142,12 +145,19 @@ sealed class Mem[T <: Data] private (t: T, length: BigInt) extends MemBase(t, le object SyncReadMem { + + type ReadUnderWrite = fir.ReadUnderWrite.Value + val Undefined = fir.ReadUnderWrite.Undefined + val ReadFirst = fir.ReadUnderWrite.Old + val WriteFirst = fir.ReadUnderWrite.New + /** Creates a sequential/synchronous-read, sequential/synchronous-write [[SyncReadMem]]. * * @param size number of elements in the memory * @param t data type of memory element */ def apply[T <: Data](size: BigInt, t: T): SyncReadMem[T] = macro MemTransform.apply[T] + def apply[T <: Data](size: BigInt, t: T, ruw: ReadUnderWrite): SyncReadMem[T] = macro MemTransform.apply_ruw[T] /** Creates a sequential/synchronous-read, sequential/synchronous-write [[SyncReadMem]]. * @@ -155,21 +165,28 @@ object SyncReadMem { * @param t data type of memory element */ def apply[T <: Data](size: Int, t: T): SyncReadMem[T] = macro MemTransform.apply[T] + def apply[T <: Data](size: Int, t: T, ruw: ReadUnderWrite): SyncReadMem[T] = macro MemTransform.apply_ruw[T] /** @group SourceInfoTransformMacro */ - def do_apply[T <: Data](size: BigInt, t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] = { + def do_apply[T <: Data](size: BigInt, t: T, ruw: ReadUnderWrite = Undefined)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] = { if (compileOptions.declaredTypeMustBeUnbound) { requireIsChiselType(t, "memory type") } val mt = t.cloneTypeFull - val mem = new SyncReadMem(mt, size) - pushCommand(DefSeqMemory(sourceInfo, mem, mt, size)) + val mem = new SyncReadMem(mt, size, ruw) + pushCommand(DefSeqMemory(sourceInfo, mem, mt, size, ruw)) mem } /** @group SourceInfoTransformMacro */ + // Alternate signatures can't use default parameter values def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] = do_apply(BigInt(size), t)(sourceInfo, compileOptions) + + /** @group SourceInfoTransformMacro */ + // Alternate signatures can't use default parameter values + def do_apply[T <: Data](size: Int, t: T, ruw: ReadUnderWrite)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] = + do_apply(BigInt(size), t, ruw)(sourceInfo, compileOptions) } /** A sequential/synchronous-read, sequential/synchronous-write memory. @@ -182,7 +199,7 @@ object SyncReadMem { * @note when multiple conflicting writes are performed on a Mem element, the * result is undefined (unlike Vec, where the last assignment wins) */ -sealed class SyncReadMem[T <: Data] private (t: T, n: BigInt) extends MemBase[T](t, n) { +sealed class SyncReadMem[T <: Data] private (t: T, n: BigInt, val readUnderWrite: SyncReadMem.ReadUnderWrite) extends MemBase[T](t, n) { def read(x: UInt, en: Bool): T = macro SourceInfoTransform.xEnArg /** @group SourceInfoTransformMacro */ diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala index 548ed294..5c1d6935 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -106,8 +106,8 @@ private[chisel3] object Converter { convert(reset, ctx), convert(init, ctx))) case e @ DefMemory(info, id, t, size) => Some(firrtl.CDefMemory(convert(info), e.name, extractType(t), size, false)) - case e @ DefSeqMemory(info, id, t, size) => - Some(firrtl.CDefMemory(convert(info), e.name, extractType(t), size, true)) + case e @ DefSeqMemory(info, id, t, size, ruw) => + Some(firrtl.CDefMemory(convert(info), e.name, extractType(t), size, true, ruw)) case e: DefMemPort[_] => Some(firrtl.CDefMPort(convert(e.sourceInfo), e.name, fir.UnknownType, e.source.fullName(ctx), Seq(convert(e.index, ctx), convert(e.clock, ctx)), convert(e.dir))) diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index e76a8d60..a16d84bb 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -2,6 +2,8 @@ package chisel3.internal.firrtl +import firrtl.{ir => fir} + import chisel3._ import chisel3.internal._ import chisel3.internal.sourceinfo.SourceInfo @@ -721,7 +723,7 @@ case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition -case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition +case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command |