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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala1
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala1
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala1
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala1
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala1
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Reg.scala1
6 files changed, 0 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index a28c4bec..5cec54c2 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -10,7 +10,6 @@ import chisel3.internal._
import chisel3.internal.Builder.pushCommand
import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
-//import chisel3.CompileOptions
/** An abstract class for data types that solely consist of (are an aggregate
* of) other Data objects.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 16bde731..efecf343 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -6,7 +6,6 @@ import chisel3.internal.Builder.pushCommand
import chisel3.internal.firrtl.Connect
import scala.language.experimental.macros
import chisel3.internal.sourceinfo._
-//import chisel3.CompileOptions
/**
* BiConnect.connect executes a bidirectional connection element-wise.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 83619fc8..3f21a34c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -9,7 +9,6 @@ import chisel3.internal.Builder.{pushCommand, pushOp}
import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
import chisel3.internal.firrtl.PrimOp.AsUIntOp
-//import chisel3.CompileOptions
sealed abstract class Direction(name: String) {
override def toString: String = name
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 55ef7491..6fb6d036 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,6 @@ import chisel3.internal.Builder._
import chisel3.internal.firrtl._
import chisel3.internal.firrtl.{Command => _, _}
import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-//import chisel3.CompileOptions
object Module {
/** A wrapper method that all Module instantiations must be wrapped in
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
index 48efda4d..ef48709b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -6,7 +6,6 @@ import chisel3.internal.Builder.pushCommand
import chisel3.internal.firrtl.Connect
import scala.language.experimental.macros
import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo, WireTransform}
-//import chisel3.CompileOptions
/**
* MonoConnect.connect executes a mono-directional connection element-wise.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index 30c2b3cd..9d380695 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -6,7 +6,6 @@ import chisel3.internal._
import chisel3.internal.Builder.pushCommand
import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
-//import chisel3.CompileOptions
object Reg {
private[core] def makeType[T <: Data](compileOptions: CompileOptions, t: T = null, next: T = null, init: T = null): T = {