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-rw-r--r--chiselFrontend/src/main/scala/chisel3/Bits.scala63
-rw-r--r--chiselFrontend/src/main/scala/chisel3/BoolFactory.scala22
-rw-r--r--chiselFrontend/src/main/scala/chisel3/Num.scala2
-rw-r--r--chiselFrontend/src/main/scala/chisel3/SIntFactory.scala30
-rw-r--r--chiselFrontend/src/main/scala/chisel3/UIntFactory.scala32
-rw-r--r--chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala3
6 files changed, 87 insertions, 65 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala
index 9939f3a2..ef9a752b 100644
--- a/chiselFrontend/src/main/scala/chisel3/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala
@@ -679,31 +679,6 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
binop(sourceInfo, SInt((this.width max that.width) + 1), SubOp, that)
}
-// This is currently a factory because both Bits and UInt inherit it.
-trait UIntFactory {
- /** Create a UInt type with inferred width. */
- def apply(): UInt = apply(Width())
- /** Create a UInt port with specified width. */
- def apply(width: Width): UInt = new UInt(width)
-
- /** Create a UInt literal with specified width. */
- protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
- val lit = ULit(value, width)
- val result = new UInt(lit.width)
- // Bind result to being an Literal
- lit.bindLitArg(result)
- }
-
- /** Create a UInt with the specified range */
- def apply(range: Range): UInt = {
- apply(range.getWidth)
- }
- /** Create a UInt with the specified range */
- def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
- apply(KnownUIntRange(range._1, range._2))
- }
-}
-
/** A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other
* integer types.
*
@@ -933,29 +908,6 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
}
}
-trait SIntFactory {
- /** Create an SInt type with inferred width. */
- def apply(): SInt = apply(Width())
- /** Create a SInt type or port with fixed width. */
- def apply(width: Width): SInt = new SInt(width)
-
- /** Create a SInt with the specified range */
- def apply(range: Range): SInt = {
- apply(range.getWidth)
- }
- /** Create a SInt with the specified range */
- def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
- apply(KnownSIntRange(range._1, range._2))
- }
-
- /** Create an SInt literal with specified width. */
- protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
- val lit = SLit(value, width)
- val result = new SInt(lit.width)
- lit.bindLitArg(result)
- }
-}
-
object SInt extends SIntFactory
sealed trait Reset extends Element with ToBoolable {
@@ -1166,21 +1118,6 @@ sealed class Bool() extends UInt(1.W) with Reset {
pushOp(DefPrim(sourceInfo, AsyncReset(), AsAsyncResetOp, ref))
}
-trait BoolFactory {
- /** Creates an empty Bool.
- */
- def apply(): Bool = new Bool()
-
- /** Creates Bool literal.
- */
- protected[chisel3] def Lit(x: Boolean): Bool = {
- val result = new Bool()
- val lit = ULit(if (x) 1 else 0, Width(1))
- // Ensure we have something capable of generating a name.
- lit.bindLitArg(result)
- }
-}
-
object Bool extends BoolFactory
package experimental {
diff --git a/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala b/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala
new file mode 100644
index 00000000..bccd6414
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.internal.firrtl.{ULit, Width}
+
+// scalastyle:off method.name
+
+trait BoolFactory {
+ /** Creates an empty Bool.
+ */
+ def apply(): Bool = new Bool()
+
+ /** Creates Bool literal.
+ */
+ protected[chisel3] def Lit(x: Boolean): Bool = {
+ val result = new Bool()
+ val lit = ULit(if (x) 1 else 0, Width(1))
+ // Ensure we have something capable of generating a name.
+ lit.bindLitArg(result)
+ }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/Num.scala b/chiselFrontend/src/main/scala/chisel3/Num.scala
index 2c63c86e..8984697f 100644
--- a/chiselFrontend/src/main/scala/chisel3/Num.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Num.scala
@@ -5,7 +5,7 @@ package chisel3
import scala.language.experimental.macros
import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-// scalastyle:off method.name line.size.limit file.size.limit
+// scalastyle:off method.name
// REVIEW TODO: Further discussion needed on what Num actually is.
diff --git a/chiselFrontend/src/main/scala/chisel3/SIntFactory.scala b/chiselFrontend/src/main/scala/chisel3/SIntFactory.scala
new file mode 100644
index 00000000..607e2e35
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/SIntFactory.scala
@@ -0,0 +1,30 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.internal.firrtl.{KnownSIntRange, NumericBound, Range, SLit, Width}
+
+// scalastyle:off method.name
+
+trait SIntFactory {
+ /** Create an SInt type with inferred width. */
+ def apply(): SInt = apply(Width())
+ /** Create a SInt type or port with fixed width. */
+ def apply(width: Width): SInt = new SInt(width)
+
+ /** Create a SInt with the specified range */
+ def apply(range: Range): SInt = {
+ apply(range.getWidth)
+ }
+ /** Create a SInt with the specified range */
+ def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
+ apply(KnownSIntRange(range._1, range._2))
+ }
+
+ /** Create an SInt literal with specified width. */
+ protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
+ val lit = SLit(value, width)
+ val result = new SInt(lit.width)
+ lit.bindLitArg(result)
+ }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/UIntFactory.scala b/chiselFrontend/src/main/scala/chisel3/UIntFactory.scala
new file mode 100644
index 00000000..a62aa493
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/UIntFactory.scala
@@ -0,0 +1,32 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.internal.firrtl.{KnownUIntRange, NumericBound, Range, ULit, Width}
+
+// scalastyle:off method.name
+
+// This is currently a factory because both Bits and UInt inherit it.
+trait UIntFactory {
+ /** Create a UInt type with inferred width. */
+ def apply(): UInt = apply(Width())
+ /** Create a UInt port with specified width. */
+ def apply(width: Width): UInt = new UInt(width)
+
+ /** Create a UInt literal with specified width. */
+ protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
+ val lit = ULit(value, width)
+ val result = new UInt(lit.width)
+ // Bind result to being an Literal
+ lit.bindLitArg(result)
+ }
+
+ /** Create a UInt with the specified range */
+ def apply(range: Range): UInt = {
+ apply(range.getWidth)
+ }
+ /** Create a UInt with the specified range */
+ def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
+ apply(KnownUIntRange(range._1, range._2))
+ }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala
index 469720e0..1f7150c8 100644
--- a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala
+++ b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala
@@ -83,4 +83,5 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
*/
object Analog {
def apply(width: Width): Analog = new Analog(width)
-} \ No newline at end of file
+}
+