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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala6
1 files changed, 5 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index b5de1317..cf015e60 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -812,7 +812,11 @@ sealed class UInt private[core] (width: Width) extends Bits(width) with Num[UInt
/** @group SourceInfoTransformMacro */
def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this =/= 0.U
/** @group SourceInfoTransformMacro */
- def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = ~this === 0.U
+ def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = width match {
+ // Generate a simpler expression if the width is known
+ case KnownWidth(w) => this === ((BigInt(1) << w) - 1).U
+ case UnknownWidth() => ~this === 0.U
+ }
/** @group SourceInfoTransformMacro */
def do_xorR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, XorReduceOp)