1 files changed, 38 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala b/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
index 015629e5..ad4050f3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
@@ -2,7 +2,7 @@
 
 package chisel3.core
 
-import chisel3.internal.InstanceId
+import chisel3.internal.{Builder, InstanceId}
 import firrtl.Transform
 import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
 
@@ -28,3 +28,40 @@ case class ChiselAnnotation(component: InstanceId, transformClass: Class[_ <: Tr
     }
   }
 }
+
+/** Marks that a signal should not be removed by Chisel and Firrtl optimization passes
+  *
+  * @example {{{
+  * class MyModule extends Module {
+  *   val io = IO(new Bundle {
+  *     val a = Input(UInt(32.W))
+  *     val b = Output(UInt(32.W))
+  *   })
+  *   io.b := io.a
+  *   val dead = io.a +% 1.U // normally dead would be pruned by DCE
+  *   dontTouch(dead) // Marking it as such will preserve it
+  * }
+  * }}}
+  *
+  * @note Calling this on Data creates an annotation that Chisel emits to a separate annotations
+  * file. This file must be passed to Firrtl independently of the .fir file.
+  * [[chisel3.Driver.execute]] will do this automatically.
+  */
+object dontTouch { // scalastyle:ignore object.name
+  /** Marks a signal to be preserved in Chisel and Firrtl
+    *
+    * @note Requires the argument to be bound to hardware
+    * @param data The signal to be marked
+    * @return Unmodified signal `data`
+    */
+  def apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T = {
+    if (compileOptions.checkSynthesizable) {
+      Binding.checkSynthesizable(data, s"$data")
+    }
+    // TODO unify with firrtl.transforms.DontTouchAnnotation
+    val anno = ChiselAnnotation(data, classOf[firrtl.Transform], "DONTtouch!")
+    Builder.annotations += anno
+    data
+  }
+}
+