diff options
Diffstat (limited to 'chiselFrontend')
3 files changed, 4 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 6d8e85a4..410f8cb4 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -75,7 +75,7 @@ abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Para } val firrtlPorts = getModulePorts map {port => Port(port, port.userDirection)} - val component = DefBlackBox(this, name, firrtlPorts, params) + val component = DefBlackBox(this, name, firrtlPorts, UserDirection.Unspecified, params) _component = Some(component) component } @@ -160,7 +160,7 @@ abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param } val firrtlPorts = namedPorts map {namedPort => Port(namedPort._2, namedPort._2.userDirection)} - val component = DefBlackBox(this, name, firrtlPorts, params) + val component = DefBlackBox(this, name, firrtlPorts, io.userDirection, params) _component = Some(component) component } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 41e09a5b..74e41895 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -19,7 +19,7 @@ object UserDirection { /** Node and its children are forced as output */ case object Output extends UserDirection - /** Node and ites children are forced as inputs + /** Node and its children are forced as inputs */ case object Input extends UserDirection /** Mainly for containers, children are flipped. diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index cca368ef..6e18792c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -274,6 +274,6 @@ abstract class Component extends Arg { def ports: Seq[Port] } case class DefModule(id: UserModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component -case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component +case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: UserDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[Annotation] = Seq.empty) |