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Diffstat (limited to 'chiselFrontend/src')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index 006670e7..f935e4ee 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -32,7 +32,7 @@ object Mem { } } -sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId with VecLike[T] { +sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId { // REVIEW TODO: make accessors (static/dynamic, read/write) combinations consistent. /** Creates a read accessor into the memory with static addressing. See the |