diff options
Diffstat (limited to 'chiselFrontend/src')
4 files changed, 32 insertions, 9 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 7fe429fa..85a57111 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -3,11 +3,20 @@ package chisel3.core import chisel3.internal.Builder.pushCommand -import chisel3.internal.firrtl.{ModuleIO, DefInvalid} +import chisel3.internal.firrtl._ +import chisel3.internal.throwException import chisel3.internal.sourceinfo.SourceInfo // TODO: remove this once we have CompileOptions threaded through the macro system. import chisel3.core.ExplicitCompileOptions.NotStrict +/** Parameters for BlackBoxes */ +sealed abstract class Param +case class IntParam(value: BigInt) extends Param +case class DoubleParam(value: Double) extends Param +case class StringParam(value: String) extends Param +/** Unquoted String */ +case class RawParam(value: String) extends Param + /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting * to RTL modules defined outside Chisel. @@ -16,12 +25,9 @@ import chisel3.core.ExplicitCompileOptions.NotStrict * {{{ * ... to be written once a spec is finalized ... * }}} + * @note The parameters API is experimental and may change */ -// REVIEW TODO: make Verilog parameters part of the constructor interface? -abstract class BlackBox extends Module { - // Don't bother taking override_clock|reset, clock/reset locked out anyway - // TODO: actually implement this. - def setVerilogParameters(s: String): Unit = {} +abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param]) extends Module { // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala // Bypass standard clock, reset, io port declaration by flattening io diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index ca391091..62b6d5ce 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -41,8 +41,16 @@ object Module { sourceInfo.makeMessage(" See " + _)) } Builder.currentModule = parent // Back to parent! + val ports = m.computePorts - val component = Component(m, m.name, ports, m._commands) + // Blackbox inherits from Module so we have to match on it first TODO fix + val component = m match { + case bb: BlackBox => + DefBlackBox(bb, bb.name, ports, bb.params) + case mod: Module => + mod._commands.prepend(DefInvalid(childSourceInfo, mod.io.ref)) // init module outputs + DefModule(mod, mod.name, ports, mod._commands) + } m._component = Some(component) Builder.components += component // Avoid referencing 'parent' in top module diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 028ce628..60ce6d5d 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -181,7 +181,10 @@ private[chisel3] object Builder { // TODO(twigg): Ideally, binding checks and new bindings would all occur here // However, rest of frontend can't support this yet. def pushCommand[T <: Command](c: T): T = { - forcedModule._commands += c + forcedModule match { + case _: BlackBox => throwException("Cannot add hardware to a BlackBox") + case m => m._commands += c + } c } def pushOp[T <: Data](cmd: DefPrim[T]): T = { diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 0f866c27..17b869f2 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -215,8 +215,14 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command -case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command +abstract class Component extends Arg { + def id: Module + def name: String + def ports: Seq[Port] +} +case class DefModule(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +case class DefBlackBox(id: Module, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component]) |