diff options
Diffstat (limited to 'chiselFrontend/src')
4 files changed, 18 insertions, 14 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 97028995..6a4d8cff 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -223,10 +223,12 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) /** Creates a dynamically indexed read or write accessor into the array. */ - def apply(idx: UInt)(implicit compileOptions: CompileOptions): T = { - Binding.checkSynthesizable(idx ,s"'idx' ($idx)") + override def apply(p: UInt): T = macro CompileOptionsTransform.pArg + + def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T = { + Binding.checkSynthesizable(p ,s"'p' ($p)") val port = gen - val i = Vec.truncateIndex(idx, length)(UnlocatableSourceInfo, compileOptions) + val i = Vec.truncateIndex(p, length)(UnlocatableSourceInfo, compileOptions) port.setRef(this, i) // Bind each element of port to being whatever the base type is @@ -243,11 +245,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) def apply(idx: Int): T = self(idx) @deprecated("Use Vec.apply instead", "chisel3") - def read(idx: UInt)(implicit compileOptions: CompileOptions): T = apply(idx) + def read(idx: UInt)(implicit compileOptions: CompileOptions): T = do_apply(idx)(compileOptions) @deprecated("Use Vec.apply instead", "chisel3") def write(idx: UInt, data: T)(implicit compileOptions: CompileOptions): Unit = { - apply(idx)(compileOptions).:=(data)(DeprecatedSourceInfo, compileOptions) + do_apply(idx)(compileOptions).:=(data)(DeprecatedSourceInfo, compileOptions) } override def cloneType: this.type = { @@ -277,7 +279,9 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) * operations. */ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { - def apply(idx: UInt)(implicit compileOptions: CompileOptions): T + def apply(p: UInt): T = macro CompileOptionsTransform.pArg + + def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T // IndexedSeq has its own hashCode/equals that we must not use override def hashCode: Int = super[HasId].hashCode @@ -325,14 +329,14 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { /** Outputs the index of the first element for which p outputs true. */ - def indexWhere(p: T => Bool): UInt = macro CompileOptionsTransform.pArg + def indexWhere(p: T => Bool): UInt = macro SourceInfoTransform.pArg def do_indexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = SeqUtils.priorityMux(indexWhereHelper(p)) /** Outputs the index of the last element for which p outputs true. */ - def lastIndexWhere(p: T => Bool): UInt = macro CompileOptionsTransform.pArg + def lastIndexWhere(p: T => Bool): UInt = macro SourceInfoTransform.pArg def do_lastIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = SeqUtils.priorityMux(indexWhereHelper(p).reverse) @@ -347,7 +351,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { * true is NOT checked (useful in cases where the condition doesn't always * hold, but the results are not used in those cases) */ - def onlyIndexWhere(p: T => Bool): UInt = macro CompileOptionsTransform.pArg + def onlyIndexWhere(p: T => Bool): UInt = macro SourceInfoTransform.pArg def do_onlyIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = SeqUtils.oneHotMux(indexWhereHelper(p)) diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index f18fb541..e8423a99 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -178,7 +178,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) */ final def pad(that: Int): this.type = macro SourceInfoTransform.thatArg - def do_pad(that: Int)(implicit sourceInfo: SourceInfo): this.type = + def do_pad(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type = binop(sourceInfo, cloneTypeWidth(this.width max Width(that)), PadOp, that) /** Returns this wire bitwise-inverted. */ @@ -509,7 +509,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) // TODO: this eventually will be renamed as toSInt, once the existing toSInt // completes its deprecation phase. final def zext(): SInt = macro SourceInfoTransform.noArg - def do_zext(implicit sourceInfo: SourceInfo): SInt = + def do_zext(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = pushOp(DefPrim(sourceInfo, SInt(width + 1), ConvertOp, ref)) /** Returns this UInt as a [[SInt]], without changing width or bit value. The diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 30e1bf97..e945cfbe 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -314,7 +314,7 @@ abstract class Data extends HasId { * @note bit widths are NOT checked, may pad or drop bits from input * @note that should have known widths */ - def asTypeOf[T <: Data](that: T): T = macro CompileOptionsTransform.thatArg + def asTypeOf[T <: Data](that: T): T = macro SourceInfoTransform.thatArg def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { val thatCloned = Wire(that.chiselCloneType) diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index db3928e3..49e96ddf 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -40,7 +40,7 @@ private[chisel3] object SeqUtils { /** Returns the data value corresponding to the first true predicate. */ - def priorityMux[T <: Data](in: Seq[(Bool, T)]): T = macro CompileOptionsTransform.inArg + def priorityMux[T <: Data](in: Seq[(Bool, T)]): T = macro SourceInfoTransform.inArg def do_priorityMux[T <: Data](in: Seq[(Bool, T)]) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { @@ -57,7 +57,7 @@ private[chisel3] object SeqUtils { * @note assumes exactly one true predicate, results undefined otherwise * FixedPoint values or aggregates containing FixedPoint values cause this optimized structure to be lost */ - def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro CompileOptionsTransform.inArg + def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro SourceInfoTransform.inArg //scalastyle:off method.length cyclomatic.complexity def do_oneHotMux[T <: Data](in: Iterable[(Bool, T)]) |