diff options
Diffstat (limited to 'chiselFrontend/src')
5 files changed, 5 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index a9f89cbc..7b0cf3f7 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -5,7 +5,7 @@ package chisel3.core import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{ModuleIO, DefInvalid} import chisel3.internal.sourceinfo.SourceInfo -import chisel3.NotStrict.NotStrictCompileOptions +import chisel3.NotStrict.CompileOptions /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 47003df0..2cfc6c6a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -9,7 +9,7 @@ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ import chisel3.internal.firrtl.{Command => _, _} import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo} -import chisel3.NotStrict.NotStrictCompileOptions +import chisel3.NotStrict.CompileOptions object Module { /** A wrapper method that all Module instantiations must be wrapped in diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 9b656dea..3191e384 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -105,7 +105,7 @@ private[chisel3] class DynamicContext(moduleCompileOptions: Option[ExplicitCompi val errors = new ErrorLog val compileOptions = moduleCompileOptions match { case Some(options: ExplicitCompileOptions) => options - case None => chisel3.NotStrict.NotStrictCompileOptions + case None => chisel3.NotStrict.CompileOptions } } diff --git a/chiselFrontend/src/main/scala/chisel3/notstrict.scala b/chiselFrontend/src/main/scala/chisel3/notstrict.scala index dc4bf807..bb390e7c 100644 --- a/chiselFrontend/src/main/scala/chisel3/notstrict.scala +++ b/chiselFrontend/src/main/scala/chisel3/notstrict.scala @@ -6,7 +6,7 @@ import chisel3.internal.ExplicitCompileOptions object NotStrict { - implicit object NotStrictCompileOptions extends ExplicitCompileOptions { + implicit object CompileOptions extends ExplicitCompileOptions { val connectFieldsMustMatch = false val declaredTypeMustBeUnbound = false val requireIOWrap = false diff --git a/chiselFrontend/src/main/scala/chisel3/strict.scala b/chiselFrontend/src/main/scala/chisel3/strict.scala index f6db8765..70240429 100644 --- a/chiselFrontend/src/main/scala/chisel3/strict.scala +++ b/chiselFrontend/src/main/scala/chisel3/strict.scala @@ -6,7 +6,7 @@ import chisel3.internal.ExplicitCompileOptions object Strict { - implicit object StrictCompileOptions extends ExplicitCompileOptions { + implicit object CompileOptions extends ExplicitCompileOptions { val connectFieldsMustMatch = true val declaredTypeMustBeUnbound = true val requireIOWrap = true |