diff options
Diffstat (limited to 'chiselFrontend/src')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Data.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 45afed94..64c84c05 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -314,7 +314,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc case Some(MemoryPortBinding(enclosure)) => s"(MemPort in ${enclosure.desiredName})" case Some(PortBinding(enclosure)) if !enclosure.isClosed => s"(IO in unelaborated ${enclosure.desiredName})" case Some(PortBinding(enclosure)) if enclosure.isClosed => - DataMirror.fullModulePorts(enclosure).find(_._2 == this) match { + DataMirror.fullModulePorts(enclosure).find(_._2 eq this) match { case Some((name, _)) => s"(IO $name in ${enclosure.desiredName})" case None => s"(IO (unknown) in ${enclosure.desiredName})" } |