diff options
Diffstat (limited to 'chiselFrontend/src/main')
7 files changed, 60 insertions, 60 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 701cf892..ca46323b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -15,10 +15,10 @@ import chisel3.internal.sourceinfo._ * of) other Data objects. */ sealed abstract class Aggregate extends Data { - private[chisel3] override def bind(target: Binding, parentDirection: UserDirection) { + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { binding = target - val resolvedDirection = UserDirection.fromParent(parentDirection, userDirection) + val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) for (child <- getElements) { child.bind(ChildBinding(this), resolvedDirection) } @@ -28,9 +28,9 @@ sealed abstract class Aggregate extends Data { direction = if (childDirections == Set()) { // Sadly, Scala can't do set matching // If empty, use my assigned direction resolvedDirection match { - case UserDirection.Unspecified | UserDirection.Flip => ActualDirection.Unspecified - case UserDirection.Output => ActualDirection.Output - case UserDirection.Input => ActualDirection.Input + case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => ActualDirection.Unspecified + case SpecifiedDirection.Output => ActualDirection.Output + case SpecifiedDirection.Input => ActualDirection.Input } } else if (childDirections == Set(ActualDirection.Unspecified)) { ActualDirection.Unspecified @@ -43,16 +43,16 @@ sealed abstract class Aggregate extends Data { ActualDirection.Bidirectional(ActualDirection.Default), ActualDirection.Bidirectional(ActualDirection.Flipped))) { resolvedDirection match { - case UserDirection.Unspecified => ActualDirection.Bidirectional(ActualDirection.Default) - case UserDirection.Flip => ActualDirection.Bidirectional(ActualDirection.Flipped) + case SpecifiedDirection.Unspecified => ActualDirection.Bidirectional(ActualDirection.Default) + case SpecifiedDirection.Flip => ActualDirection.Bidirectional(ActualDirection.Flipped) case _ => throw new RuntimeException("Unexpected forced Input / Output") } } else { this match { // Anything flies in compatibility mode case t: Record if !t.compileOptions.dontAssumeDirectionality => resolvedDirection match { - case UserDirection.Unspecified => ActualDirection.Bidirectional(ActualDirection.Default) - case UserDirection.Flip => ActualDirection.Bidirectional(ActualDirection.Flipped) + case SpecifiedDirection.Unspecified => ActualDirection.Bidirectional(ActualDirection.Default) + case SpecifiedDirection.Flip => ActualDirection.Bidirectional(ActualDirection.Flipped) case _ => ActualDirection.Bidirectional(ActualDirection.Default) } case _ => @@ -275,11 +275,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) // Reconstruct the resolvedDirection (in Aggregate.bind), since it's not stored. // It may not be exactly equal to that value, but the results are the same. val reconstructedResolvedDirection = direction match { - case ActualDirection.Input => UserDirection.Input - case ActualDirection.Output => UserDirection.Output + case ActualDirection.Input => SpecifiedDirection.Input + case ActualDirection.Output => SpecifiedDirection.Output case ActualDirection.Bidirectional(ActualDirection.Default) | ActualDirection.Unspecified => - UserDirection.Unspecified - case ActualDirection.Bidirectional(ActualDirection.Flipped) => UserDirection.Flip + SpecifiedDirection.Unspecified + case ActualDirection.Bidirectional(ActualDirection.Flipped) => SpecifiedDirection.Flip } // TODO port technically isn't directly child of this data structure, but the result of some // muxes / demuxes. However, this does make access consistent with the top-level bindings. diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 6f638a13..f61ca5a9 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -18,13 +18,13 @@ import chisel3.internal.firrtl.PrimOp._ * uses are for representing primitive data types, like integers and bits. */ abstract class Element(private[chisel3] val width: Width) extends Data { - private[chisel3] override def bind(target: Binding, parentDirection: UserDirection) { + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { binding = target - val resolvedDirection = UserDirection.fromParent(parentDirection, userDirection) + val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) direction = resolvedDirection match { - case UserDirection.Unspecified | UserDirection.Flip => ActualDirection.Unspecified - case UserDirection.Output => ActualDirection.Output - case UserDirection.Input => ActualDirection.Input + case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => ActualDirection.Unspecified + case SpecifiedDirection.Output => ActualDirection.Output + case SpecifiedDirection.Input => ActualDirection.Input } } @@ -1063,9 +1063,9 @@ final class Analog private (width: Width) extends Element(width) { // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) - private[chisel3] override def bind(target: Binding, parentDirection: UserDirection) { - UserDirection.fromParent(parentDirection, userDirection) match { - case UserDirection.Unspecified | UserDirection.Flip => + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { + SpecifiedDirection.fromParent(parentDirection, specifiedDirection) match { + case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => case x => throwException(s"Analog may not have explicit direction, got '$x'") } val targetTopBinding = target match { diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 410f8cb4..f5e0d5ba 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -74,8 +74,8 @@ abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Para id._onModuleClose } - val firrtlPorts = getModulePorts map {port => Port(port, port.userDirection)} - val component = DefBlackBox(this, name, firrtlPorts, UserDirection.Unspecified, params) + val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)} + val component = DefBlackBox(this, name, firrtlPorts, SpecifiedDirection.Unspecified, params) _component = Some(component) component } @@ -159,8 +159,8 @@ abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param id._onModuleClose } - val firrtlPorts = namedPorts map {namedPort => Port(namedPort._2, namedPort._2.userDirection)} - val component = DefBlackBox(this, name, firrtlPorts, io.userDirection, params) + val firrtlPorts = namedPorts map {namedPort => Port(namedPort._2, namedPort._2.specifiedDirection)} + val component = DefBlackBox(this, name, firrtlPorts, io.specifiedDirection, params) _component = Some(component) component } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 66f16294..be1fe753 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -11,22 +11,22 @@ import chisel3.internal.sourceinfo._ /** User-specified directions. */ -sealed abstract class UserDirection -object UserDirection { +sealed abstract class SpecifiedDirection +object SpecifiedDirection { /** Default user direction, also meaning 'not-flipped' */ - case object Unspecified extends UserDirection + case object Unspecified extends SpecifiedDirection /** Node and its children are forced as output */ - case object Output extends UserDirection + case object Output extends SpecifiedDirection /** Node and its children are forced as inputs */ - case object Input extends UserDirection + case object Input extends SpecifiedDirection /** Mainly for containers, children are flipped. */ - case object Flip extends UserDirection + case object Flip extends SpecifiedDirection - def flip(dir: UserDirection) = dir match { + def flip(dir: SpecifiedDirection) = dir match { case Unspecified => Flip case Flip => Unspecified case Output => Input @@ -36,12 +36,12 @@ object UserDirection { /** Returns the effective UserDirection of this node given the parent's effective UserDirection * and the user-specified UserDirection of this node. */ - def fromParent(parentDirection: UserDirection, thisDirection: UserDirection) = + def fromParent(parentDirection: SpecifiedDirection, thisDirection: SpecifiedDirection) = (parentDirection, thisDirection) match { - case (UserDirection.Output, _) => UserDirection.Output - case (UserDirection.Input, _) => UserDirection.Input - case (UserDirection.Unspecified, thisDirection) => thisDirection - case (UserDirection.Flip, thisDirection) => UserDirection.flip(thisDirection) + case (SpecifiedDirection.Output, _) => SpecifiedDirection.Output + case (SpecifiedDirection.Input, _) => SpecifiedDirection.Input + case (SpecifiedDirection.Unspecified, thisDirection) => thisDirection + case (SpecifiedDirection.Flip, thisDirection) => SpecifiedDirection.flip(thisDirection) } } @@ -78,7 +78,7 @@ object debug { // scalastyle:ignore object.name */ object DataMirror { def widthOf(target: Data): Width = target.width - def userDirectionOf(target: Data): UserDirection = target.userDirection + def specifiedDirectionOf(target: Data): SpecifiedDirection = target.specifiedDirection def directionOf(target: Data): ActualDirection = { requireIsHardware(target, "node requested directionality on") target.direction @@ -147,21 +147,21 @@ private[core] object cloneSupertype { object Input { def apply[T<:Data](source: T): T = { val out = source.cloneType - out.userDirection = UserDirection.Input + out.specifiedDirection = SpecifiedDirection.Input out } } object Output { def apply[T<:Data](source: T): T = { val out = source.cloneType - out.userDirection = UserDirection.Output + out.specifiedDirection = SpecifiedDirection.Output out } } object Flipped { def apply[T<:Data](source: T): T = { val out = source.cloneType - out.userDirection = UserDirection.flip(source.userDirection) + out.specifiedDirection = SpecifiedDirection.flip(source.specifiedDirection) out } } @@ -183,18 +183,18 @@ abstract class Data extends HasId { } // User-specified direction, local at this node only. - // Note that the actual direction of this node can differ from child and parent userDirection. - private var _userDirection: UserDirection = UserDirection.Unspecified - private[chisel3] def userDirection: UserDirection = _userDirection - private[core] def userDirection_=(direction: UserDirection) = { - if (_userDirection != UserDirection.Unspecified) { + // Note that the actual direction of this node can differ from child and parent specifiedDirection. + private var _specifiedDirection: SpecifiedDirection = SpecifiedDirection.Unspecified + private[chisel3] def specifiedDirection: SpecifiedDirection = _specifiedDirection + private[core] def specifiedDirection_=(direction: SpecifiedDirection) = { + if (_specifiedDirection != SpecifiedDirection.Unspecified) { this match { // Anything flies in compatibility mode case t: Record if !t.compileOptions.dontAssumeDirectionality => - case _ => throw Binding.RebindingException(s"Attempted reassignment of user direction to $this") + case _ => throw Binding.RebindingException(s"Attempted reassignment of user-specified direction to $this") } } - _userDirection = direction + _specifiedDirection = direction } /** This overwrites a relative UserDirection with an explicit one, and is used to implement @@ -202,11 +202,11 @@ abstract class Data extends HasId { * DO NOT USE OUTSIDE THIS PURPOSE. THIS OPERATION IS DANGEROUS! */ private[core] def _assignCompatibilityExplicitDirection: Unit = { - (this, _userDirection) match { + (this, _specifiedDirection) match { case (_: Analog, _) => // nothing to do - case (_, UserDirection.Unspecified) => _userDirection = UserDirection.Output - case (_, UserDirection.Flip) => _userDirection = UserDirection.Input - case (_, UserDirection.Input | UserDirection.Output) => // nothing to do + case (_, SpecifiedDirection.Unspecified) => _specifiedDirection = SpecifiedDirection.Output + case (_, SpecifiedDirection.Flip) => _specifiedDirection = SpecifiedDirection.Input + case (_, SpecifiedDirection.Input | SpecifiedDirection.Output) => // nothing to do } } @@ -236,7 +236,7 @@ abstract class Data extends HasId { * node is the top-level. * binding and direction are valid after this call completes. */ - private[chisel3] def bind(target: Binding, parentDirection: UserDirection = UserDirection.Unspecified) + private[chisel3] def bind(target: Binding, parentDirection: SpecifiedDirection = SpecifiedDirection.Unspecified) // Both _direction and _resolvedUserDirection are saved versions of computed variables (for // efficiency, avoid expensive recomputation of frequent operations). @@ -319,7 +319,7 @@ abstract class Data extends HasId { def chiselCloneType: this.type = { val clone = this.cloneType // get a fresh object, without bindings // Only the top-level direction needs to be fixed up, cloneType should do the rest - clone.userDirection = userDirection + clone.specifiedDirection = specifiedDirection clone } final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 558e6432..dfb9081c 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -232,16 +232,16 @@ abstract class BaseModule extends HasId { data match { case data: Element if insideCompat => data._assignCompatibilityExplicitDirection case data: Element => // Not inside a compatibility Bundle, nothing to be done - case data: Aggregate => data.userDirection match { + case data: Aggregate => data.specifiedDirection match { // Recurse into children to ensure explicit direction set somewhere - case UserDirection.Unspecified | UserDirection.Flip => data match { + case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => data match { case record: Record => val compatRecord = !record.compileOptions.dontAssumeDirectionality record.getElements.foreach(assignCompatDir(_, compatRecord)) case vec: Vec[_] => vec.getElements.foreach(assignCompatDir(_, insideCompat)) } - case UserDirection.Input | UserDirection.Output => // forced assign, nothing to do + case SpecifiedDirection.Input | SpecifiedDirection.Output => // forced assign, nothing to do } } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala index 5207ef04..8b176c3b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala @@ -64,7 +64,7 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions) id._onModuleClose } - val firrtlPorts = getModulePorts map {port => Port(port, port.userDirection)} + val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)} _firrtlPorts = Some(firrtlPorts) // Generate IO invalidation commands to initialize outputs as unused diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 6e18792c..05cde071 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -266,7 +266,7 @@ case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends C case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command -case class Port(id: Data, dir: UserDirection) +case class Port(id: Data, dir: SpecifiedDirection) case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command abstract class Component extends Arg { def id: BaseModule @@ -274,6 +274,6 @@ abstract class Component extends Arg { def ports: Seq[Port] } case class DefModule(id: UserModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component -case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: UserDirection, params: Map[String, Param]) extends Component +case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[Annotation] = Seq.empty) |