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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala9
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala12
2 files changed, 12 insertions, 9 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 94d808a4..9cca5d9d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -210,15 +210,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
def do_asSInt(implicit sourceInfo: SourceInfo): SInt
- /** Reinterpret cast to an UInt.
- *
- * @note value not guaranteed to be preserved: for example, a SInt of width
- * 3 and value -1 (0b111) would become an UInt with value 7
- */
- final def asUInt(): UInt = macro SourceInfoTransform.noArg
-
- def do_asUInt(implicit sourceInfo: SourceInfo): UInt
-
/** Reinterpret cast to Bits. */
final def asBits(): Bits = macro SourceInfoTransform.noArg
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index d5704369..d31e50ff 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -114,6 +114,18 @@ abstract class Data(dirArg: Direction) extends HasId {
*/
@deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3")
def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
+
+ /** Reinterpret cast to UInt.
+ *
+ * @note value not guaranteed to be preserved: for example, a SInt of width
+ * 3 and value -1 (0b111) would become an UInt with value 7
+ * @note Aggregates are recursively packed with the first element appearing
+ * in the least-significant bits of the result.
+ */
+ final def asUInt(): UInt = macro SourceInfoTransform.noArg
+
+ def do_asUInt(implicit sourceInfo: SourceInfo): UInt =
+ SeqUtils.do_asUInt(this.flatten)(sourceInfo)
}
object Wire {