diff options
Diffstat (limited to 'chiselFrontend/src/main')
5 files changed, 6 insertions, 9 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala index 43a74192..92f602c4 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala @@ -60,7 +60,7 @@ object assert { // scalastyle:ignore object.name case None => s"Assertion failed\n at $escLine\n" } printf.printfWithoutReset(fmt, data:_*) - pushCommand(Stop(sourceInfo, Node(Builder.forcedClock), 1)) + pushCommand(Stop(sourceInfo, Builder.forcedClock.ref, 1)) } } @@ -81,7 +81,7 @@ object stop { // scalastyle:ignore object.name /** Terminate execution with a failure code. */ def apply(code: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { when (!Module.reset.toBool) { - pushCommand(Stop(sourceInfo, Node(Builder.forcedClock), code)) + pushCommand(Stop(sourceInfo, Builder.forcedClock.ref, code)) } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index adf97dbe..eae605c1 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -67,9 +67,6 @@ sealed abstract class Bits(width: Width) // Arguments for: self-checking code (can't do arithmetic on bits) // Arguments against: generates down to a FIRRTL UInt anyways - // If this is a literal, setRef so that we don't allocate a name - litArg.foreach(setRef) - // Only used for in a few cases, hopefully to be removed private[core] def cloneTypeWidth(width: Width): this.type diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index 27ce6f3f..73bf3708 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -99,7 +99,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi val port = pushCommand( DefMemPort(sourceInfo, - t.cloneTypeFull, Node(this), dir, i.ref, Node(Builder.forcedClock)) + t.cloneTypeFull, Node(this), dir, i.ref, Builder.forcedClock.ref) ).id // Bind each element of port to being a MemoryPort port.bind(MemoryPortBinding(Builder.forcedUserModule)) diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala index 99d0e06e..bfab57d8 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala @@ -93,7 +93,7 @@ object printf { // scalastyle:ignore object.name private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { val clock = Builder.forcedClock - pushCommand(Printf(sourceInfo, Node(clock), pable)) + pushCommand(Printf(sourceInfo, clock.ref, pable)) } private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = printfWithoutReset(Printable.pack(fmt, data:_*)) diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala index 16244d12..11611c82 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala @@ -84,8 +84,8 @@ object RegInit { requireIsChiselType(t, "reg type") } val reg = t.cloneTypeFull - val clock = Node(Builder.forcedClock) - val reset = Node(Builder.forcedReset) + val clock = Builder.forcedClock.ref + val reset = Builder.forcedReset.ref reg.bind(RegBinding(Builder.forcedUserModule)) requireIsHardware(init, "reg initializer") |