summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala
diff options
context:
space:
mode:
Diffstat (limited to 'chiselFrontend/src/main/scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala8
1 files changed, 8 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 8c874070..9115d1ba 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -227,6 +227,14 @@ object Wire {
object Clock {
def apply(): Clock = new Clock
+ def apply(dir: Direction): Clock = {
+ val result = apply()
+ dir match {
+ case Direction.Input => Input(result)
+ case Direction.Output => Output(result)
+ case Direction.Unspecified => result
+ }
+ }
}
// TODO: Document this.