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-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index e39b007e..0641686c 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -42,6 +42,7 @@ object PrimOp {
val ConvertOp = PrimOp("cvt")
val AsUIntOp = PrimOp("asUInt")
val AsSIntOp = PrimOp("asSInt")
+ val AsClockOp = PrimOp("asClock")
}
abstract class Arg {