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Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 18ab8dc2..35d2c0f6 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -277,7 +277,7 @@ object VecInit { require(!elts.isEmpty) elts.foreach(requireIsHardware(_, "vec element")) - val vec = Wire(new Vec(cloneSupertype(elts, "Vec"), elts.length)) + val vec = Wire(Vec(elts.length, cloneSupertype(elts, "Vec"))) // TODO: try to remove the logic for this mess elts.head.direction match { |