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Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 450f5b58..24dabcbe 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -119,7 +119,7 @@ extends HasId { } // Port definitions need to know input or output at top-level. // By FIRRTL semantics, 'flipped' becomes an Input - val direction = if(Data.isFlipped(port)) Direction.Input else Direction.Output + val direction = if(Data.isFirrtlFlipped(port)) Direction.Input else Direction.Output firrtl.Port(port, direction) } |