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Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 2426ae78..8093babc 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -94,7 +94,7 @@ extends HasId { private[chisel3] def addId(d: HasId) { _ids += d } private[core] def ports: Seq[(String,Data)] = Vector( - ("clk", clock), ("reset", reset), ("io", io) + ("clock", clock), ("reset", reset), ("io", io) ) private[core] def computePorts = for((name, port) <- ports) yield { |