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Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 5a4f6abb..2f365dd7 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -75,6 +75,8 @@ object Module { def clock: Clock = Builder.forcedClock /** Returns the implicit Reset */ def reset: Reset = Builder.forcedReset + /** Returns the current Module */ + def currentModule: Option[BaseModule] = Builder.currentModule } /** Abstract base class for Modules, an instantiable organizational unit for RTL. |