diff options
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index 558dea7a..e435860e 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -25,12 +25,12 @@ private[chisel3] object SeqUtils { } } - /** Outputs the number of elements that === Bool(true). + /** Outputs the number of elements that === true.B. */ def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match { - case 0 => UInt(0) + case 0 => 0.U case 1 => in.head case n => count(in take n/2) +& count(in drop n/2) } @@ -57,7 +57,7 @@ private[chisel3] object SeqUtils { if (in.tail.isEmpty) { in.head._2 } else { - val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0)) + val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, 0.U) val width = in.map(_._2.width).reduce(_ max _) in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } |
