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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Reg.scala11
1 files changed, 9 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index 57979be0..30abe5e5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -16,12 +16,19 @@ object Reg {
}
t.chiselCloneType
} else if (next ne null) {
- next.cloneTypeWidth(Width())
+ (next match {
+ case next: Bits => next.cloneTypeWidth(Width())
+ case _ => next.chiselCloneType
+ }).asInstanceOf[T]
+
} else if (init ne null) {
init.litArg match {
// For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k
case Some(lit) if lit.forcedWidth => init.chiselCloneType
- case _ => init.cloneTypeWidth(Width())
+ case _ => (init match {
+ case init: Bits => init.cloneTypeWidth(Width())
+ case _ => init.chiselCloneType
+ }).asInstanceOf[T]
}
} else {
throwException("cannot infer type")