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Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/RawModule.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/RawModule.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala index 397debcb..b224d9a3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala @@ -146,7 +146,8 @@ abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions) val reset: Reset = IO(Input(Bool())) // Setup ClockAndReset - Builder.currentClockAndReset = Some(ClockAndReset(clock, reset)) + Builder.currentClock = Some(clock) + Builder.currentReset = Some(reset) private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { implicit val sourceInfo = UnlocatableSourceInfo |