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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Mux.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mux.scala b/chiselFrontend/src/main/scala/chisel3/core/Mux.scala
index f01c59ca..e4ef001f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mux.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mux.scala
@@ -26,10 +26,10 @@ object Mux {
def do_apply[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo,
compileOptions: CompileOptions): T = {
- Binding.checkSynthesizable(cond, s"'cond' ($cond)")
- Binding.checkSynthesizable(con, s"'con' ($con)")
- Binding.checkSynthesizable(alt, s"'alt' ($alt)")
+ requireIsHardware(cond, "mux condition")
+ requireIsHardware(con, "mux true value")
+ requireIsHardware(alt, "mux false value")
val d = cloneSupertype(Seq(con, alt), "Mux")
pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, con.ref, alt.ref))
}
-} \ No newline at end of file
+}