1 files changed, 56 insertions, 29 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Module.scala b/chiselFrontend/src/main/scala/chisel3/Module.scala
index c8527f34..a6f682a8 100644
--- a/chiselFrontend/src/main/scala/chisel3/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Module.scala
@@ -14,8 +14,7 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo}
 import chisel3.experimental.BaseModule
-
-import _root_.firrtl.annotations.{CircuitName, ModuleName}
+import _root_.firrtl.annotations.{ModuleName, ModuleTarget, IsModule}
 
 object Module extends SourceInfoDoc {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -180,15 +179,21 @@ package experimental {
     private[chisel3] val _namespace = Namespace.empty
     private val _ids = ArrayBuffer[HasId]()
     private[chisel3] def addId(d: HasId) {
-      require(!_closed, "Can't write to module after module close")
-      _ids += d
+      if (Builder.aspectModule(this).isDefined) {
+        aspectModule(this).get.addId(d)
+      } else {
+        require(!_closed, "Can't write to module after module close")
+        _ids += d
+      }
     }
+
     protected def getIds = {
       require(_closed, "Can't get ids before module close")
       _ids.toSeq
     }
 
     private val _ports = new ArrayBuffer[Data]()
+
     // getPorts unfortunately already used for tester compatibility
     protected[chisel3] def getModulePorts = {
       require(_closed, "Can't get ports before module close")
@@ -198,6 +203,7 @@ package experimental {
     // These methods allow checking some properties of ports before the module is closed,
     // mainly for compatibility purposes.
     protected def portsContains(elem: Data): Boolean = _ports contains elem
+
     protected def portsSize: Int = _ports.size
 
     /** Generates the FIRRTL Component (Module or Blackbox) of this Module.
@@ -227,19 +233,38 @@ package experimental {
     }
 
     /** Returns a FIRRTL ModuleName that references this object
+      *
       * @note Should not be called until circuit elaboration is complete
       */
-    final def toNamed: ModuleName = ModuleName(this.name, CircuitName(this.circuitName))
+    @deprecated("toNamed API is deprecated -- use toTarget instead", "3.2")
+    final def toNamed: ModuleName = toTarget.toNamed
+
+    /** Returns a FIRRTL ModuleTarget that references this object
+      *
+      * @note Should not be called until circuit elaboration is complete
+      */
+    final def toTarget: ModuleTarget = ModuleTarget(this.circuitName, this.name)
+
+    /** Returns a FIRRTL ModuleTarget that references this object
+      *
+      * @note Should not be called until circuit elaboration is complete
+      */
+    final def toAbsoluteTarget: IsModule = {
+      _parent match {
+        case Some(parent) => parent.toAbsoluteTarget.instOf(this.instanceName, toTarget.module)
+        case None => toTarget
+      }
+    }
 
     /**
-     * Internal API. Returns a list of this module's generated top-level ports as a map of a String
-     * (FIRRTL name) to the IO object. Only valid after the module is closed.
-     *
-     * Note: for BlackBoxes (but not ExtModules), this returns the contents of the top-level io
-     * object, consistent with what is emitted in FIRRTL.
-     *
-     * TODO: Use SeqMap/VectorMap when those data structures become available.
-     */
+      * Internal API. Returns a list of this module's generated top-level ports as a map of a String
+      * (FIRRTL name) to the IO object. Only valid after the module is closed.
+      *
+      * Note: for BlackBoxes (but not ExtModules), this returns the contents of the top-level io
+      * object, consistent with what is emitted in FIRRTL.
+      *
+      * TODO: Use SeqMap/VectorMap when those data structures become available.
+      */
     private[chisel3] def getChiselPorts: Seq[(String, Data)] = {
       require(_closed, "Can't get ports before module close")
       _component.get.ports.map { port =>
@@ -313,31 +338,33 @@ package experimental {
           }
         }
       }
+
       assignCompatDir(iodef, false)
 
       iodef.bind(PortBinding(this))
       _ports += iodef
     }
+
     /** Private accessor for _bindIoInPlace */
     private[chisel3] def bindIoInPlace(iodef: Data): Unit = _bindIoInPlace(iodef)
 
     /**
-     * This must wrap the datatype used to set the io field of any Module.
-     * i.e. All concrete modules must have defined io in this form:
-     * [lazy] val io[: io type] = IO(...[: io type])
-     *
-     * Items in [] are optional.
-     *
-     * The granted iodef must be a chisel type and not be bound to hardware.
-     *
-     * Also registers a Data as a port, also performing bindings. Cannot be called once ports are
-     * requested (so that all calls to ports will return the same information).
-     * Internal API.
-     *
-     * TODO(twigg): Specifically walk the Data definition to call out which nodes
-     * are problematic.
-     */
-    protected def IO[T<:Data](iodef: T): T = chisel3.experimental.IO.apply(iodef) // scalastyle:ignore method.name
+      * This must wrap the datatype used to set the io field of any Module.
+      * i.e. All concrete modules must have defined io in this form:
+      * [lazy] val io[: io type] = IO(...[: io type])
+      *
+      * Items in [] are optional.
+      *
+      * The granted iodef must be a chisel type and not be bound to hardware.
+      *
+      * Also registers a Data as a port, also performing bindings. Cannot be called once ports are
+      * requested (so that all calls to ports will return the same information).
+      * Internal API.
+      *
+      * TODO(twigg): Specifically walk the Data definition to call out which nodes
+      * are problematic.
+      */
+    protected def IO[T <: Data](iodef: T): T = chisel3.experimental.IO.apply(iodef) // scalastyle:ignore method.name
 
     //
     // Internal Functions