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Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/Bits.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/Bits.scala | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala index 57ce98d2..96eb74a4 100644 --- a/chiselFrontend/src/main/scala/chisel3/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala @@ -581,13 +581,9 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U final def xorR(): Bool = macro SourceInfoTransform.noArg /** @group SourceInfoTransformMacro */ - def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this =/= 0.U + def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, OrReduceOp) /** @group SourceInfoTransformMacro */ - def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = width match { - // Generate a simpler expression if the width is known - case KnownWidth(w) => this === ((BigInt(1) << w) - 1).U - case UnknownWidth() => ~this === 0.U - } + def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, AndReduceOp) /** @group SourceInfoTransformMacro */ def do_xorR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, XorReduceOp) |