diff options
Diffstat (limited to 'chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala index 91dcf5d2..62784cee 100644 --- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -3,6 +3,7 @@ package Chisel.internal.firrtl import Chisel._ import Chisel.internal._ +import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo} case class PrimOp(val name: String) { override def toString: String = name @@ -142,29 +143,31 @@ object MemPortDirection { object INFER extends MemPortDirection("infer") } -abstract class Command +abstract class Command { + def sourceInfo: SourceInfo +} abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } -case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition -case class DefInvalid(arg: Arg) extends Command -case class DefWire(id: Data) extends Definition -case class DefReg(id: Data, clock: Arg) extends Definition -case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition -case class DefMemory(id: HasId, t: Data, size: Int) extends Definition -case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition -case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition -case class DefInstance(id: Module, ports: Seq[Port]) extends Definition -case class WhenBegin(pred: Arg) extends Command -case class WhenEnd() extends Command -case class Connect(loc: Node, exp: Arg) extends Command -case class BulkConnect(loc1: Node, loc2: Node) extends Command -case class ConnectInit(loc: Node, exp: Arg) extends Command -case class Stop(clk: Arg, ret: Int) extends Command +case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition +case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command +case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition +case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition +case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: Int) extends Definition +case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: Int) extends Definition +case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition +case class DefInstance(sourceInfo: SourceInfo, id: Module, ports: Seq[Port]) extends Definition +case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command +case class WhenEnd(sourceInfo: SourceInfo) extends Command +case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command +case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +case class Stop(sourceInfo: SourceInfo, clk: Arg, ret: Int) extends Command case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) -case class Printf(clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command { +case class Printf(sourceInfo: SourceInfo, clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command { require(formatIn.forall(c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values") def format: String = { def escaped(x: Char) = { |