1 files changed, 22 insertions, 4 deletions
diff --git a/AbstractModuleStandalone.scala b/AbstractModuleStandalone.scala
index a896b1f7..2e43d3c9 100644
--- a/AbstractModuleStandalone.scala
+++ b/AbstractModuleStandalone.scala
@@ -1,4 +1,5 @@
 import chisel3._
+import chisel3.stage.ChiselStage
 
 object TypeArithmetic {
   implicit val f1: SomeTypeContainer => SomeTypeContainer => SomeTypeContainer = (a: SomeTypeContainer) => (b: SomeTypeContainer) => new SomeTypeContainer(a.i+b.i)
@@ -15,6 +16,7 @@ object TypeArithmetic {
 case class SomeTypeContainer(i: Int)
 
 object AbstractModuleStandalone {
+  class SomeModule extends Module
   def main(args: Array[String]): Unit = {
     val foo: Int = 1
     val bar: SomeTypeContainer = SomeTypeContainer(2)
@@ -26,10 +28,26 @@ object AbstractModuleStandalone {
     
     import MetaConnect._
     import TypeArithmetic._
-    bar makeConnection foo makeConnection bar makeConnection bar
-    bar makeConnection baz makeConnection foo
+    val barfoobarbar = bar makeConnection foo makeConnection bar makeConnection bar
+    val barbazfoo = bar makeConnection baz makeConnection foo
 
-    abaz makeConnection afoo
-    afoo makeConnection abar
+    val abazafoo = abaz makeConnection afoo
+    val afooabar = afoo makeConnection abar
+
+    val topIface = Seq(abazafoo, afooabar)
+    def topBody(iface: Seq[AbstractInterface[_]]): () => Module = {
+      val k = () => new SomeModule {
+        iface.foreach { x => x.params match {
+          case some: UInt => x.params.asInstanceOf[UInt] := 19.U
+          case _ => 
+        }}
+     } 
+     k
+    }
+
+    println(ChiselStage.emitFirrtl({
+      (new AbstractModule(Seq(abazafoo, afooabar))(topBody)).comp()
+    }))
   }
+
 }