diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 6 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 30 |
2 files changed, 35 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 197135d7..1eef5d69 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -174,9 +174,13 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) /** A trait for [[Vec]]s containing common hardware generators for collection * operations. */ -trait VecLike[T <: Data] extends collection.IndexedSeq[T] { +trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId { def apply(idx: UInt): T + // IndexedSeq has its own hashCode/equals that we must not use + override def hashCode: Int = super[HasId].hashCode + override def equals(that: Any): Boolean = super[HasId].equals(that) + @deprecated("Use Vec.apply instead", "chisel3") def read(idx: UInt): T diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 5239c6ba..943d9e4b 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -41,6 +41,32 @@ class ShiftRegisterTester(n: Int) extends BasicTester { } } +class FunBundle extends Bundle { + val stuff = UInt(width = 10) +} + +class ZeroModule extends Module { + val io = new Bundle { + val mem = UInt(width = 10) + val interrupts = Vec(2, Bool()).asInput + val mmio_axi = Vec(0, new FunBundle) + val mmio_ahb = Vec(0, new FunBundle).flip + } + + io.mmio_axi <> io.mmio_ahb + + io.mem := UInt(0) + when (io.interrupts(0)) { io.mem := UInt(1) } + when (io.interrupts(1)) { io.mem := UInt(2) } +} + +class ZeroTester extends BasicTester { + val foo = Module(new ZeroModule) + foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) } + assert (foo.io.mem === UInt(2)) + stop() +} + class VecSpec extends ChiselPropSpec { property("Vecs should be assignable") { forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) => @@ -55,4 +81,8 @@ class VecSpec extends ChiselPropSpec { property("Regs of vecs should be usable as shift registers") { forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } } } + + property("Dual empty Vectors") { + assertTesterPasses{ new ZeroTester } + } } |