diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Bits.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/Chisel/Bits.scala index 27790336..ce177ef1 100644 --- a/chiselFrontend/src/main/scala/Chisel/Bits.scala +++ b/chiselFrontend/src/main/scala/Chisel/Bits.scala @@ -155,7 +155,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: /** Returns the contents of this wire as a [[Vec]] of [[Bool]]s. */ - def toBools: Vec[Bool] = Vec.tabulate(this.getWidth)(i => this(i)) + def toBools: Seq[Bool] = Seq.tabulate(this.getWidth)(i => this(i)) /** Reinterpret cast to a SInt. * |