diff options
5 files changed, 34 insertions, 7 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 9d8a9061..5e88560c 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -19,6 +19,8 @@ sealed abstract class Aggregate extends Data { private[core] def width: Width = flatten.map(_.width).reduce(_ + _) private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) + + override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten) } object Vec { diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index c4161a32..a5d954b6 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -282,9 +282,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) pushOp(DefPrim(sourceInfo, UInt(w), ConcatOp, this.ref, that.ref)) } - @deprecated("Use asUInt, which does the same thing but makes the reinterpret cast more explicit", "chisel3") - override def toBits: UInt = do_asUInt(DeprecatedSourceInfo) - override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = { val res = Wire(this, null).asInstanceOf[this.type] res := that diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index bd2e9065..86858e5d 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -254,7 +254,7 @@ abstract class Data extends HasId { * * This performs the inverse operation of fromBits(Bits). */ - @deprecated("Use asUInt, which does the same thing but makes the reinterpret cast more explicit", "chisel3") + @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3") def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo) /** Reinterpret cast to UInt. diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 53d46e93..5b38ff6e 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -24,6 +24,27 @@ class BundleWire(n: Int) extends Module { } } +class BundleToUnitTester extends BasicTester { + val bundle1 = Wire(new Bundle { + val a = UInt(width = 4) + val b = UInt(width = 4) + }) + val bundle2 = Wire(new Bundle { + val a = UInt(width = 2) + val b = UInt(width = 6) + }) + + // 0b00011011 split as 0001 1011 and as 00 011011 + bundle1.a := 1.U + bundle1.b := 11.U + bundle2.a := 0.U + bundle2.b := 27.U + + assert(bundle1.asUInt() === bundle2.asUInt()) + + stop() +} + class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester { val dut = Module(new BundleWire(n)) dut.io.in.x := UInt(x) @@ -43,3 +64,10 @@ class BundleWireSpec extends ChiselPropSpec { } } } + +class BundleToUIntSpec extends ChiselPropSpec { + property("Bundles with same data but different, underlying elements should compare as UInt") { + assertTesterPasses( new BundleToUnitTester ) + } +} + diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index c5447610..0d5a2188 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -23,9 +23,9 @@ class TabulateTester(n: Int) extends BasicTester { val x = Vec(Array.tabulate(n){ i => UInt(i * 2) }) val u = Vec.tabulate(n)(i => UInt(i*2)) - assert(v.toBits === x.toBits) - assert(v.toBits === u.toBits) - assert(x.toBits === u.toBits) + assert(v.asUInt() === x.asUInt()) + assert(v.asUInt() === u.asUInt()) + assert(x.asUInt() === u.asUInt()) stop() } |