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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala2
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala10
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Clock.scala2
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala13
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala2
-rw-r--r--src/main/scala/chisel3/util/Conditional.scala4
-rw-r--r--src/test/scala/chiselTests/LiteralExtractorSpec.scala36
7 files changed, 33 insertions, 36 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 9bb24e43..b1e86ea7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -62,7 +62,7 @@ sealed abstract class Aggregate extends Data {
}
}
- def litToBigIntOption: Option[BigInt] = ??? // TODO implement me
+ override def litOption = ??? // TODO implement me
// Returns the LitArg of a Bits object.
// Internal API for Bundle literals, to copy the LitArg of argument literals into the top map.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index a8ebab1b..b54b5e11 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -86,7 +86,7 @@ sealed abstract class Bits(width: Width)
case _ => None
}
- override def litToBigIntOption: Option[BigInt] = litArgOption.map(_.num)
+ override def litOption: Option[BigInt] = litArgOption.map(_.num)
private[core] def litIsForcedWidth: Option[Boolean] = litArgOption.map(_.forcedWidth)
// provide bits-specific literal handling functionality here
@@ -764,7 +764,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
new Bool().asInstanceOf[this.type]
}
- def litToBooleanOption: Option[Boolean] = litToBigIntOption.map {
+ def litToBooleanOption: Option[Boolean] = litOption.map {
case intVal if intVal == 1 => true
case intVal if intVal == 0 => false
case intVal => throwException(s"Boolean with unexpected literal value $intVal")
@@ -851,7 +851,7 @@ sealed class FixedPoint private (width: Width, val binaryPoint: BinaryPoint)
case _ => this badConnect that
}
- def litToDoubleOption: Option[Double] = litToBigIntOption.map { intVal =>
+ def litToDoubleOption: Option[Double] = litOption.map { intVal =>
val multiplier = math.pow(2, binaryPoint.get)
intVal.toDouble / multiplier
}
@@ -1125,6 +1125,8 @@ final class Analog private (width: Width) extends Element(width) {
private[core] override def typeEquivalent(that: Data): Boolean =
that.isInstanceOf[Analog] && this.width == that.width
+ override def litOption = None
+
def cloneType: this.type = new Analog(width).asInstanceOf[this.type]
// Used to enforce single bulk connect of Analog types, multi-attach is still okay
@@ -1153,8 +1155,6 @@ final class Analog private (width: Width) extends Element(width) {
binding = target
}
- override def litToBigIntOption = None
-
override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
throwException("Analog does not support asUInt")
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
index 55f76160..b728075b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
@@ -23,7 +23,7 @@ sealed class Clock extends Element(Width(1)) {
case _ => super.badConnect(that)(sourceInfo)
}
- override def litToBigIntOption = None
+ override def litOption = None
/** Not really supported */
def toPrintable: Printable = PString("CLOCK")
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 466f976e..171a2bff 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -385,29 +385,26 @@ abstract class Data extends HasId with NamedComponent {
final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
@chiselRuntimeDeprecated
- @deprecated("litArg is deprecated, use litToBigIntOption or litTo*Option", "chisel3.2")
+ @deprecated("litArg is deprecated, use litOption or litTo*Option", "chisel3.2")
def litArg(): Option[LitArg] = topBindingOpt match {
case Some(ElementLitBinding(litArg)) => Some(litArg)
case Some(BundleLitBinding(litMap)) => None // this API does not support Bundle literals
case _ => None
}
@chiselRuntimeDeprecated
- @deprecated("litValue deprecated, use litToBigInt or litTo*", "chisel3.2")
- def litValue(): BigInt = litArg.get.num
- @chiselRuntimeDeprecated
- @deprecated("isLit is deprecated, use litToBigIntOption or litTo*Option", "chisel3.2")
+ @deprecated("isLit is deprecated, use litOption.isDefined", "chisel3.2")
def isLit(): Boolean = litArg.isDefined
/**
* If this is a literal that is representable as bits, returns the value as a BigInt.
* If not a literal, or not representable as bits (for example, is or contains Analog), returns None.
*/
- def litToBigIntOption: Option[BigInt]
+ def litOption(): Option[BigInt]
/**
* Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
*/
- def litToBigInt: BigInt = litToBigIntOption.get
+ def litValue(): BigInt = litOption.get
/** Returns the width, in bits, if currently known.
* @throws java.util.NoSuchElementException if the width is not known. */
@@ -518,7 +515,7 @@ object DontCare extends Element(width = UnknownWidth()) {
bind(DontCareBinding(), SpecifiedDirection.Output)
override def cloneType = DontCare
- override def litToBigIntOption = None
+ override def litOption = None
def toPrintable: Printable = PString("DONTCARE")
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 3a3a7061..6ff08bea 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -75,7 +75,7 @@ object BitPat {
*/
def apply(x: UInt): BitPat = {
val len = if (x.isWidthKnown) x.getWidth else 0
- apply("b" + x.litToBigInt.toString(2).reverse.padTo(len, "0").reverse.mkString)
+ apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString)
}
}
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 1d2805ad..bf2d4268 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -28,8 +28,8 @@ class SwitchContext[T <: Bits](cond: T, whenContext: Option[WhenContext], lits:
def is(v: Iterable[T])(block: => Unit): SwitchContext[T] = {
if (!v.isEmpty) {
val newLits = v.map { w =>
- require(w.litToBigIntOption.isDefined, "is condition must be literal")
- val value = w.litToBigInt
+ require(w.litOption.isDefined, "is condition must be literal")
+ val value = w.litValue
require(!lits.contains(value), "all is conditions must be mutually exclusive!")
value
}
diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
index 8354297b..e3cf2587 100644
--- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala
+++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
@@ -9,24 +9,24 @@ import chisel3.testers.BasicTester
import org.scalatest._
class LiteralExtractorSpec extends ChiselFlatSpec {
- "litToBigInt" should "return the literal value" in {
- assert(0.U.litToBigInt === BigInt(0))
- assert(1.U.litToBigInt === BigInt(1))
- assert(42.U.litToBigInt === BigInt(42))
- assert(42.U.litToBigInt === 42.U.litToBigInt)
+ "litValue" should "return the literal value" in {
+ assert(0.U.litValue === BigInt(0))
+ assert(1.U.litValue === BigInt(1))
+ assert(42.U.litValue === BigInt(42))
+ assert(42.U.litValue === 42.U.litValue)
- assert(0.S.litToBigInt === BigInt(0))
- assert(-1.S.litToBigInt === BigInt(-1))
- assert(-42.S.litToBigInt === BigInt(-42))
+ assert(0.S.litValue === BigInt(0))
+ assert(-1.S.litValue === BigInt(-1))
+ assert(-42.S.litValue === BigInt(-42))
- assert(true.B.litToBigInt === BigInt(1))
- assert(false.B.litToBigInt === BigInt(0))
+ assert(true.B.litValue === BigInt(1))
+ assert(false.B.litValue === BigInt(0))
- assert(1.25.F(2.BP).litToBigInt === BigInt("101", 2))
- assert(2.25.F(2.BP).litToBigInt === BigInt("1001", 2))
+ assert(1.25.F(2.BP).litValue === BigInt("101", 2))
+ assert(2.25.F(2.BP).litValue === BigInt("1001", 2))
- assert(-1.25.F(2.BP).litToBigInt === BigInt("-101", 2))
- assert(-2.25.F(2.BP).litToBigInt === BigInt("-1001", 2))
+ assert(-1.25.F(2.BP).litValue === BigInt("-101", 2))
+ assert(-2.25.F(2.BP).litValue === BigInt("-1001", 2))
}
"litToBoolean" should "return the literal value" in {
@@ -46,10 +46,10 @@ class LiteralExtractorSpec extends ChiselFlatSpec {
assert(1.25.F(1.BP).litToDouble == 1.5)
}
- "litToBigIntOption" should "return None for non-literal hardware" in {
+ "litOption" should "return None for non-literal hardware" in {
elaborate { new RawModule {
val a = Wire(UInt())
- assert(a.litToBigIntOption == None)
+ assert(a.litOption == None)
}}
}
@@ -114,8 +114,8 @@ class LiteralExtractorSpec extends ChiselFlatSpec {
}
}
val myBundleLiteral = (new MyBundle).Lit(42.U, true.B)
- assert(myBundleLiteral.a.litToBigInt == 42)
- assert(myBundleLiteral.b.litToBigInt == 1)
+ assert(myBundleLiteral.a.litValue == 42)
+ assert(myBundleLiteral.b.litValue == 1)
assert(myBundleLiteral.b.litToBoolean == true)
}
}