diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/UIntOps.scala | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 4b35c163..1f592f38 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -508,7 +508,7 @@ class AutoClonetypeException(message: String) extends ChiselException(message, n * } * }}} */ -class Bundle(implicit compileOptions: CompileOptions) extends Record { +abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { override def className = "Bundle" /** The collection of [[Data]] diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 7feee96f..d24c3b4d 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -69,7 +69,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks it should "successfully compile a complete module" in { class Dummy extends Module { // The following just checks that we can create objects with nothing more than the Chisel compatibility package. - val io = new Bundle + val io = new Bundle {} val data = UInt(width = 3) new ArbiterIO(data, 2) shouldBe a [ArbiterIO[_]] new LockingRRArbiter(data, 2, 2, None) shouldBe a [LockingRRArbiter[_]] diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index 490af22b..149ec3c4 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -92,7 +92,7 @@ class BadBoolConversion extends Module { } class NegativeShift(t: => Bits) extends Module { - val io = IO(new Bundle) + val io = IO(new Bundle {}) Reg(t) >> -1 } |