2 files changed, 33 insertions, 8 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 4c4c0c01..b512ed75 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -32,7 +32,10 @@ object Module {
 
     val parent = Builder.currentModule
     val whenDepth: Int = Builder.whenDepth
+
+    // Save then clear clock and reset to prevent leaking scope, must be set again in the Module
     val clockAndReset: Option[ClockAndReset] = Builder.currentClockAndReset
+    Builder.currentClockAndReset = None
 
     // Execute the module, this has the following side effects:
     //   - set currentModule
@@ -108,7 +111,7 @@ abstract class BaseModule extends HasId {
     require(_closed, "Can't get ports before module close")
     _ports.toSeq
   }
-  
+
   // These methods allow checking some properties of ports before the module is closed,
   // mainly for compatibility purposes.
   protected def portsContains(elem: Data): Boolean = _ports contains elem
diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
index 180a1c04..b864a669 100644
--- a/src/test/scala/chiselTests/RawModuleSpec.scala
+++ b/src/test/scala/chiselTests/RawModuleSpec.scala
@@ -28,12 +28,12 @@ class PlusOneModule extends Module {
   io.out := io.in + 1.asUInt
 }
 
-class RawModuleWithImpliitModule extends RawModule {
+class RawModuleWithImplicitModule extends RawModule {
   val in  = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
   val clk = IO(Input(Clock()))
   val rst = IO(Input(Bool()))
-  
+
   withClockAndReset(clk, rst) {
     val plusModule = Module(new PlusOneModule)
     plusModule.io.in := in
@@ -42,7 +42,7 @@ class RawModuleWithImpliitModule extends RawModule {
 }
 
 class ImplicitModuleInRawModuleTester extends BasicTester {
-  val plusModule = Module(new RawModuleWithImpliitModule)
+  val plusModule = Module(new RawModuleWithImplicitModule)
   plusModule.clk := clock
   plusModule.rst := reset
   plusModule.in := 42.U
@@ -50,16 +50,38 @@ class ImplicitModuleInRawModuleTester extends BasicTester {
   stop()
 }
 
+class RawModuleWithDirectImplicitModule extends RawModule {
+  val plusModule = Module(new PlusOneModule)
+}
+
+class ImplicitModuleDirectlyInRawModuleTester extends BasicTester {
+  val plusModule = Module(new RawModuleWithDirectImplicitModule)
+  stop()
+}
+
 class RawModuleSpec extends ChiselFlatSpec {
   "RawModule" should "elaborate" in {
-    elaborate { new RawModuleWithImpliitModule }
+    elaborate { new RawModuleWithImplicitModule }
   }
-  
+
   "RawModule" should "work" in {
     assertTesterPasses({ new RawModuleTester })
   }
-  
+
   "ImplicitModule in a withClock block in a RawModule" should "work" in {
     assertTesterPasses({ new ImplicitModuleInRawModuleTester })
   }
-}
\ No newline at end of file
+
+
+  "ImplicitModule directly in a RawModule" should "fail" in {
+    intercept[chisel3.internal.ChiselException] {
+      elaborate { new RawModuleWithDirectImplicitModule }
+    }
+  }
+
+  "ImplicitModule directly in a RawModule in an ImplicitModule" should "fail" in {
+    intercept[chisel3.internal.ChiselException] {
+      elaborate { new ImplicitModuleDirectlyInRawModuleTester }
+    }
+  }
+}