diff options
10 files changed, 84 insertions, 43 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index ac3553b9..c201a12c 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -3,7 +3,7 @@ package chisel3.stage import firrtl.{ir => fir, AnnotationSeq, EmittedFirrtlCircuitAnnotation, EmittedVerilogCircuitAnnotation} -import firrtl.options.{Dependency, Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.{Dependency, Phase, PhaseManager, Shell, Stage, StageError, StageMain} import firrtl.options.phases.DeletedWrapper import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlCli} import firrtl.options.Viewer.view @@ -13,7 +13,12 @@ import chisel3.internal.{firrtl => cir, ErrorLog} import java.io.{StringWriter, PrintWriter} -class ChiselStage extends Stage with PreservesAll[Phase] { +class ChiselStage extends Stage { + + override def prerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala index 3c90e551..682a3974 100644 --- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala +++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala @@ -4,14 +4,17 @@ package chisel3.stage.phases import chisel3.stage.ChiselCircuitAnnotation import firrtl.AnnotationSeq -import firrtl.options.{Dependency, OutputAnnotationFileAnnotation, Phase, PreservesAll} +import firrtl.options.{Dependency, OutputAnnotationFileAnnotation, Phase} /** Adds an [[firrtl.options.OutputAnnotationFileAnnotation]] if one does not exist. This replicates old behavior where * an output annotation file was always written. */ -class AddImplicitOutputAnnotationFile extends Phase with PreservesAll[Phase] { +class AddImplicitOutputAnnotationFile extends Phase { - override val prerequisites = Seq(Dependency[Elaborate]) + override def prerequisites = Seq(Dependency[Elaborate]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations .collectFirst{ case _: OutputAnnotationFileAnnotation => annotations } diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala index 56cc5147..d511377a 100644 --- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala +++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala @@ -3,16 +3,19 @@ package chisel3.stage.phases import firrtl.AnnotationSeq -import firrtl.options.{Dependency, Phase, PreservesAll} +import firrtl.options.{Dependency, Phase} import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation} /** Add a output file for a Chisel circuit, derived from the top module in the circuit, if no * [[ChiselOutputFileAnnotation]] already exists. */ -class AddImplicitOutputFile extends Phase with PreservesAll[Phase] { +class AddImplicitOutputFile extends Phase { - override val prerequisites = Seq(Dependency[Elaborate]) + override def prerequisites = Seq(Dependency[Elaborate]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.collectFirst{ case _: ChiselOutputFileAnnotation => annotations }.getOrElse{ diff --git a/src/main/scala/chisel3/stage/phases/Checks.scala b/src/main/scala/chisel3/stage/phases/Checks.scala index e2563e06..f9813f8e 100644 --- a/src/main/scala/chisel3/stage/phases/Checks.scala +++ b/src/main/scala/chisel3/stage/phases/Checks.scala @@ -6,14 +6,17 @@ import chisel3.stage.{ChiselOutputFileAnnotation, NoRunFirrtlCompilerAnnotation, import firrtl.AnnotationSeq import firrtl.annotations.Annotation -import firrtl.options.{Dependency, OptionsException, Phase, PreservesAll} +import firrtl.options.{Dependency, OptionsException, Phase} /** Sanity checks an [[firrtl.AnnotationSeq]] before running the main [[firrtl.options.Phase]]s of * [[chisel3.stage.ChiselStage]]. */ -class Checks extends Phase with PreservesAll[Phase] { +class Checks extends Phase { - override val dependents = Seq(Dependency[Elaborate]) + override def prerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq(Dependency[Elaborate]) + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = { val noF, st, outF = collection.mutable.ListBuffer[Annotation]() diff --git a/src/main/scala/chisel3/stage/phases/Convert.scala b/src/main/scala/chisel3/stage/phases/Convert.scala index 0ba1a5c9..d105c32c 100644 --- a/src/main/scala/chisel3/stage/phases/Convert.scala +++ b/src/main/scala/chisel3/stage/phases/Convert.scala @@ -6,7 +6,7 @@ import chisel3.experimental.RunFirrtlTransform import chisel3.internal.firrtl.Converter import chisel3.stage.ChiselCircuitAnnotation import firrtl.{AnnotationSeq, Transform} -import firrtl.options.{Dependency, Phase, PreservesAll} +import firrtl.options.{Dependency, Phase} import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} /** This prepares a [[ChiselCircuitAnnotation]] for compilation with FIRRTL. This does three things: @@ -14,9 +14,12 @@ import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} * - Extracts all [[firrtl.annotations.Annotation]]s from the [[chisel3.internal.firrtl.Circuit]] * - Generates any needed [[RunFirrtlTransformAnnotation]]s from extracted [[firrtl.annotations.Annotation]]s */ -class Convert extends Phase with PreservesAll[Phase] { +class Convert extends Phase { - override val prerequisites = Seq(Dependency[Elaborate]) + override def prerequisites = Seq(Dependency[Elaborate]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap { case a: ChiselCircuitAnnotation => diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala index 776e39b3..1ec92827 100644 --- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala +++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala @@ -4,7 +4,7 @@ package chisel3.stage.phases import firrtl.{AnnotationSeq, ExecutionOptionsManager, HasFirrtlOptions} import firrtl.annotations.NoTargetAnnotation -import firrtl.options.{Dependency, OptionsException, OutputAnnotationFileAnnotation, Phase, PreservesAll, Unserializable} +import firrtl.options.{Dependency, OptionsException, OutputAnnotationFileAnnotation, Phase, Unserializable} import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation} import firrtl.stage.phases.DriverCompatibility.TopNameAnnotation @@ -25,9 +25,12 @@ object DriverCompatibility { * the correct behavior before a circuit has been elaborated. * @note the output suffix is unspecified and will be set by the underlying [[firrtl.EmittedComponent]] */ - private [chisel3] class AddImplicitOutputFile extends Phase with PreservesAll[Phase] { + private [chisel3] class AddImplicitOutputFile extends Phase { - override val dependents = Seq(Dependency[chisel3.stage.ChiselStage]) + override def prerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.ChiselStage]) + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = { val hasOutputFile = annotations @@ -49,9 +52,12 @@ object DriverCompatibility { * correct behavior before a circuit has been elaborated. * @note the output suffix is unspecified and will be set by [[firrtl.options.phases.WriteOutputAnnotations]] */ - private[chisel3] class AddImplicitOutputAnnotationFile extends Phase with PreservesAll[Phase] { + private[chisel3] class AddImplicitOutputAnnotationFile extends Phase { - override val dependents = Seq(Dependency[chisel3.stage.ChiselStage]) + override def prerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.ChiselStage]) + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations @@ -73,18 +79,24 @@ object DriverCompatibility { * situations where you need to do something between Chisel compilation and FIRRTL compilations, e.g., update a * mutable data structure. */ - private[chisel3] class DisableFirrtlStage extends Phase with PreservesAll[Phase] { + private[chisel3] class DisableFirrtlStage extends Phase { - override val dependents = Seq(Dependency[ChiselStage]) + override def prerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq(Dependency[ChiselStage]) + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations } .getOrElse { Seq(RunFirrtlCompilerAnnotation, NoRunFirrtlCompilerAnnotation) ++ annotations } } - private[chisel3] class ReEnableFirrtlStage extends Phase with PreservesAll[Phase] { + private[chisel3] class ReEnableFirrtlStage extends Phase { - override val prerequisites = Seq(Dependency[DisableFirrtlStage], Dependency[ChiselStage]) + override def prerequisites = Seq(Dependency[DisableFirrtlStage], Dependency[ChiselStage]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations .collectFirst { case RunFirrtlCompilerAnnotation => @@ -106,11 +118,12 @@ object DriverCompatibility { * This is intended to be run between [[chisel3.stage.ChiselStage ChiselStage]] and [[firrtl.stage.FirrtlStage]] if * you want to have backwards compatibility with an [[firrtl.ExecutionOptionsManager]]. */ - private[chisel3] class MutateOptionsManager extends Phase with PreservesAll[Phase] { + private[chisel3] class MutateOptionsManager extends Phase { - override val prerequisites = Seq(Dependency[chisel3.stage.ChiselStage]) - - override val dependents = Seq(Dependency[ReEnableFirrtlStage]) + override def prerequisites = Seq(Dependency[chisel3.stage.ChiselStage]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq(Dependency[ReEnableFirrtlStage]) + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = { @@ -135,11 +148,12 @@ object DriverCompatibility { /** A [[Phase]] that lets us run * @todo a better solution than the current state hack below may be needed */ - private [chisel3] class FirrtlPreprocessing extends Phase with PreservesAll[Phase] { - - override val prerequisites = Seq(Dependency[ChiselStage], Dependency[MutateOptionsManager], Dependency[ReEnableFirrtlStage]) + private [chisel3] class FirrtlPreprocessing extends Phase { - override val dependents = Seq(Dependency[MaybeFirrtlStage]) + override def prerequisites = Seq(Dependency[ChiselStage], Dependency[MutateOptionsManager], Dependency[ReEnableFirrtlStage]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq(Dependency[MaybeFirrtlStage]) + override def invalidates(a: Phase) = false private val phases = Seq( new firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile, diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala index 0f92c480..816b8478 100644 --- a/src/main/scala/chisel3/stage/phases/Elaborate.scala +++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala @@ -9,11 +9,16 @@ import chisel3.internal.ErrorLog import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOptions} import firrtl.AnnotationSeq import firrtl.options.Viewer.view -import firrtl.options.{OptionsException, Phase, PreservesAll} +import firrtl.options.{OptionsException, Phase} /** Elaborate all [[chisel3.stage.ChiselGeneratorAnnotation]]s into [[chisel3.stage.ChiselCircuitAnnotation]]s. */ -class Elaborate extends Phase with PreservesAll[Phase] { +class Elaborate extends Phase { + + override def prerequisites = Seq.empty + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap { case a: ChiselGeneratorAnnotation => a.elaborate diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala index 7fb9ef91..96a698ae 100644 --- a/src/main/scala/chisel3/stage/phases/Emitter.scala +++ b/src/main/scala/chisel3/stage/phases/Emitter.scala @@ -24,15 +24,14 @@ import java.io.{File, FileWriter} */ class Emitter extends Phase { - override val prerequisites = + override def prerequisites = Seq( Dependency[Elaborate], Dependency[AddImplicitOutputFile], Dependency[AddImplicitOutputAnnotationFile], Dependency[MaybeAspectPhase] ) - + override def optionalPrerequisites = Seq.empty override def optionalPrerequisiteOf = Seq(Dependency[Convert]) - - override def invalidates(phase: Phase): Boolean = false + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = { val copts = view[ChiselOptions](annotations) diff --git a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala index 7c1bb423..7aff4701 100644 --- a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala +++ b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala @@ -4,13 +4,16 @@ package chisel3.stage.phases import chisel3.aop.Aspect import firrtl.AnnotationSeq -import firrtl.options.{Dependency, Phase, PreservesAll} +import firrtl.options.{Dependency, Phase} /** Run [[AspectPhase]] if a [[chisel3.aop.Aspect]] is present. */ -class MaybeAspectPhase extends Phase with PreservesAll[Phase] { +class MaybeAspectPhase extends Phase { - override val prerequisites = Seq(Dependency[Elaborate]) + override def prerequisites = Seq(Dependency[Elaborate]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = { if(annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) { diff --git a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala index 4dd9669a..03f1fb53 100644 --- a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala +++ b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala @@ -5,14 +5,17 @@ package chisel3.stage.phases import chisel3.stage.NoRunFirrtlCompilerAnnotation import firrtl.AnnotationSeq -import firrtl.options.{Dependency, Phase, PreservesAll} +import firrtl.options.{Dependency, Phase} import firrtl.stage.FirrtlStage /** Run [[firrtl.stage.FirrtlStage]] if a [[chisel3.stage.NoRunFirrtlCompilerAnnotation]] is not present. */ -class MaybeFirrtlStage extends Phase with PreservesAll[Phase] { +class MaybeFirrtlStage extends Phase { - override val prerequisites = Seq(Dependency[Convert]) + override def prerequisites = Seq(Dependency[Convert]) + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Seq.empty + override def invalidates(a: Phase) = false def transform(annotations: AnnotationSeq): AnnotationSeq = annotations .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations } |