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-rw-r--r--src/test/scala/chiselTests/ChiselSpec.scala3
-rw-r--r--src/test/scala/chiselTests/MultiAssign.scala38
2 files changed, 41 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 8cd6dd0c..da68b0cb 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -17,6 +17,9 @@ trait ChiselRunners extends Assertions {
def assertTesterPasses(t: => BasicTester, additionalVResources: Seq[String] = Seq()): Unit = {
assert(runTester(t, additionalVResources))
}
+ def assertTesterFails(t: => BasicTester, additionalVResources: Seq[String] = Seq()): Unit = {
+ assert(!runTester(t, additionalVResources))
+ }
def elaborate(t: => Module): Unit = Driver.elaborate(() => t)
}
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
new file mode 100644
index 00000000..2f464123
--- /dev/null
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -0,0 +1,38 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import Chisel._
+import Chisel.testers.BasicTester
+
+class LastAssignTester() extends BasicTester {
+ val cnt = Counter(2)
+
+ val test = Wire(UInt(width=4))
+ assert(test === UInt(7)) // allow read references before assign references
+
+ test := UInt(13)
+ assert(test === UInt(7)) // output value should be position-independent
+
+ test := UInt(7)
+ assert(test === UInt(7)) // this obviously should work
+
+ when(cnt.value === UInt(1)) {
+ stop()
+ }
+}
+
+class ReassignmentTester() extends BasicTester {
+ val test = UInt(15)
+ test := UInt(7)
+}
+
+class MultiAssignSpec extends ChiselFlatSpec {
+ "The last assignment" should "be used when multiple assignments happen" in {
+ assertTesterPasses{ new LastAssignTester }
+ }
+ "Reassignments to non-wire types" should "be disallowed" in {
+ assertTesterFails{ new ReassignmentTester }
+ }
+}