3 files changed, 22 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index b1e86ea7..3dbce379 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -77,9 +77,9 @@ sealed abstract class Aggregate extends Data {
     // If the source is a DontCare, generate a DefInvalid for the sink,
     //  otherwise, issue a Connect.
     if (that == DontCare) {
-      pushCommand(DefInvalid(sourceInfo, this.lref))
+      pushCommand(DefInvalid(sourceInfo, Node(this)))
     } else {
-      pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
+      pushCommand(BulkConnect(sourceInfo, Node(this), Node(that)))
     }
   }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index b67c3fe3..c3645700 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -36,9 +36,9 @@ abstract class Element(private[chisel3] val width: Width) extends Data {
     // If the source is a DontCare, generate a DefInvalid for the sink,
     //  otherwise, issue a Connect.
     if (that == DontCare) {
-      pushCommand(DefInvalid(sourceInfo, this.lref))
+      pushCommand(DefInvalid(sourceInfo, Node(this)))
     } else {
-      pushCommand(Connect(sourceInfo, this.lref, that.ref))
+      pushCommand(Connect(sourceInfo, Node(this), that.ref))
     }
   }
 }
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index d24c3b4d..eb38cab1 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -304,4 +304,22 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
     }
   }
 
+  "Mux return value" should "be able to be used on the RHS" in {
+    import Chisel._
+    elaborate(new Module {
+      val gen = new Bundle { val foo = UInt(width = 8) }
+      val io = new Bundle {
+        val a = Vec(2, UInt(width = 8)).asInput
+        val b = Vec(2, UInt(width = 8)).asInput
+        val c = gen.asInput
+        val d = gen.asInput
+        val en = Bool(INPUT)
+        val y = Vec(2, UInt(width = 8)).asOutput
+        val z = gen.asOutput
+      }
+      io.y := Mux(io.en, io.a, io.b)
+      io.z := Mux(io.en, io.c, io.d)
+    })
+  }
+
 }