2 files changed, 31 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala
index b926a15c..c301ff98 100644
--- a/src/main/scala/chisel3/verilog.scala
+++ b/src/main/scala/chisel3/verilog.scala
@@ -4,7 +4,29 @@ import chisel3.stage.ChiselStage
 import firrtl.AnnotationSeq
 
 object getVerilogString {
+
+  /**
+    * Returns a string containing the Verilog for the module specified by
+    * the target.
+    *
+    * @param gen the module to be converted to Verilog
+    * @return a string containing the Verilog for the module specified by
+    *         the target
+    */
   def apply(gen: => RawModule): String = ChiselStage.emitVerilog(gen)
+
+  /**
+    * Returns a string containing the Verilog for the module specified by
+    * the target accepting arguments and annotations
+    *
+    * @param gen the module to be converted to Verilog
+    * @param args arguments to be passed to the compiler
+    * @param annotations annotations to be passed to the compiler
+    * @return a string containing the Verilog for the module specified by
+    *         the target
+    */
+  def apply(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String =
+    (new ChiselStage).emitVerilog(gen, args, annotations)
 }
 
 object emitVerilog {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 13dbe1e9..b0fece3b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -18,6 +18,8 @@ class SimpleIO extends Bundle {
 
 class PlusOne extends Module {
   val io = IO(new SimpleIO)
+  val myReg = RegInit(0.U(8.W))
+  dontTouch(myReg)
   io.out := io.in + 1.asUInt
 }
 
@@ -267,6 +269,13 @@ class ModuleSpec extends ChiselPropSpec with Utils {
   property("getVerilogString(new PlusOne() should produce a valid Verilog string") {
     val s = getVerilogString(new PlusOne())
     assert(s.contains("assign io_out = io_in + 32'h1"))
+    assert(s.contains("RANDOMIZE_REG_INIT"))
+  }
+
+  property("getVerilogString(new PlusOne() should produce a valid Verilog string with arguments") {
+    val s = getVerilogString(new PlusOne(), Array("--emission-options=disableRegisterRandomization"))
+    assert(s.contains("assign io_out = io_in + 32'h1"))
+    assert(!s.contains("RANDOMIZE_REG_INIT"))
   }
 
   property("emitVerilog((new PlusOne()..) shall produce a valid Verilog file in a subfolder") {