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-rw-r--r--src/main/scala/Chisel/testers/Driver.scala5
-rw-r--r--src/test/scala/ChiselTests/BitsOps.scala1
-rw-r--r--src/test/scala/ChiselTests/BundleWire.scala1
-rw-r--r--src/test/scala/ChiselTests/ComplexAssign.scala1
-rw-r--r--src/test/scala/ChiselTests/Counter.scala1
-rw-r--r--src/test/scala/ChiselTests/Decoder.scala1
-rw-r--r--src/test/scala/ChiselTests/DirChange.scala1
-rw-r--r--src/test/scala/ChiselTests/EnableShiftRegister.scala1
-rw-r--r--src/test/scala/ChiselTests/GCD.scala1
-rw-r--r--src/test/scala/ChiselTests/LFSR16.scala1
-rw-r--r--src/test/scala/ChiselTests/MemorySearch.scala1
-rw-r--r--src/test/scala/ChiselTests/ModuleVec.scala1
-rw-r--r--src/test/scala/ChiselTests/ModuleWire.scala1
-rw-r--r--src/test/scala/ChiselTests/Mul.scala1
-rw-r--r--src/test/scala/ChiselTests/Outer.scala1
-rw-r--r--src/test/scala/ChiselTests/Pads.scala1
-rw-r--r--src/test/scala/ChiselTests/RegisterVecShift.scala1
-rw-r--r--src/test/scala/ChiselTests/Risc.scala1
-rw-r--r--src/test/scala/ChiselTests/Rom.scala1
-rw-r--r--src/test/scala/ChiselTests/SIntOps.scala1
-rw-r--r--src/test/scala/ChiselTests/Stack.scala1
-rw-r--r--src/test/scala/ChiselTests/Tbl.scala1
-rw-r--r--src/test/scala/ChiselTests/UIntOps.scala1
-rw-r--r--src/test/scala/ChiselTests/VecApp.scala1
-rw-r--r--src/test/scala/ChiselTests/VecShiftRegister.scala1
-rw-r--r--src/test/scala/ChiselTests/VendingMachine.scala1
-rw-r--r--src/test/scala/ChiselTests/main.scala1
27 files changed, 31 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/testers/Driver.scala b/src/main/scala/Chisel/testers/Driver.scala
index 294c77c1..69fddb41 100644
--- a/src/main/scala/Chisel/testers/Driver.scala
+++ b/src/main/scala/Chisel/testers/Driver.scala
@@ -97,3 +97,8 @@ object TesterDriver {
}
}
+
+// This should go away.
+object chiselMainTest {
+ def apply[T <: Module](args: Array[String], gen: () => T)(tester: T => Tester[T]): T = ???
+}
diff --git a/src/test/scala/ChiselTests/BitsOps.scala b/src/test/scala/ChiselTests/BitsOps.scala
index bfcbaf49..068ea7b8 100644
--- a/src/test/scala/ChiselTests/BitsOps.scala
+++ b/src/test/scala/ChiselTests/BitsOps.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class BitsOps extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/BundleWire.scala b/src/test/scala/ChiselTests/BundleWire.scala
index 50bb60e2..5d6af2aa 100644
--- a/src/test/scala/ChiselTests/BundleWire.scala
+++ b/src/test/scala/ChiselTests/BundleWire.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Coord extends Bundle {
val x = UInt(width = 32)
diff --git a/src/test/scala/ChiselTests/ComplexAssign.scala b/src/test/scala/ChiselTests/ComplexAssign.scala
index 886a2a7e..88c79d56 100644
--- a/src/test/scala/ChiselTests/ComplexAssign.scala
+++ b/src/test/scala/ChiselTests/ComplexAssign.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Complex[T <: Data](val re: T, val im: T) extends Bundle {
override def cloneType: this.type =
diff --git a/src/test/scala/ChiselTests/Counter.scala b/src/test/scala/ChiselTests/Counter.scala
index cab61c53..55fbf6db 100644
--- a/src/test/scala/ChiselTests/Counter.scala
+++ b/src/test/scala/ChiselTests/Counter.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
object Counter {
def wrapAround(n: UInt, max: UInt) =
diff --git a/src/test/scala/ChiselTests/Decoder.scala b/src/test/scala/ChiselTests/Decoder.scala
index 0a295678..147c1b80 100644
--- a/src/test/scala/ChiselTests/Decoder.scala
+++ b/src/test/scala/ChiselTests/Decoder.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
object Insts {
def ADD = BitPat("b0000000??????????000?????0110011")
diff --git a/src/test/scala/ChiselTests/DirChange.scala b/src/test/scala/ChiselTests/DirChange.scala
index 882d4844..babe6c06 100644
--- a/src/test/scala/ChiselTests/DirChange.scala
+++ b/src/test/scala/ChiselTests/DirChange.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class DirChange extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/EnableShiftRegister.scala b/src/test/scala/ChiselTests/EnableShiftRegister.scala
index 49825271..a0b2e88d 100644
--- a/src/test/scala/ChiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/ChiselTests/EnableShiftRegister.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class EnableShiftRegister extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/GCD.scala b/src/test/scala/ChiselTests/GCD.scala
index 2702aaec..164a1cfe 100644
--- a/src/test/scala/ChiselTests/GCD.scala
+++ b/src/test/scala/ChiselTests/GCD.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class GCD extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/LFSR16.scala b/src/test/scala/ChiselTests/LFSR16.scala
index 2683247f..ac9d3d8d 100644
--- a/src/test/scala/ChiselTests/LFSR16.scala
+++ b/src/test/scala/ChiselTests/LFSR16.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class LFSR16 extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/MemorySearch.scala b/src/test/scala/ChiselTests/MemorySearch.scala
index e58005c2..5f830d7c 100644
--- a/src/test/scala/ChiselTests/MemorySearch.scala
+++ b/src/test/scala/ChiselTests/MemorySearch.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class MemorySearch extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/ModuleVec.scala b/src/test/scala/ChiselTests/ModuleVec.scala
index 9d76760d..26b4ed5e 100644
--- a/src/test/scala/ChiselTests/ModuleVec.scala
+++ b/src/test/scala/ChiselTests/ModuleVec.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class PlusOne extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/ModuleWire.scala b/src/test/scala/ChiselTests/ModuleWire.scala
index 13e74a06..50d40292 100644
--- a/src/test/scala/ChiselTests/ModuleWire.scala
+++ b/src/test/scala/ChiselTests/ModuleWire.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Inc extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/Mul.scala b/src/test/scala/ChiselTests/Mul.scala
index 9f7c604c..fe61705e 100644
--- a/src/test/scala/ChiselTests/Mul.scala
+++ b/src/test/scala/ChiselTests/Mul.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
import scala.collection.mutable.ArrayBuffer
class Mul(val w: Int) extends Module {
diff --git a/src/test/scala/ChiselTests/Outer.scala b/src/test/scala/ChiselTests/Outer.scala
index 8e206f90..4a20544d 100644
--- a/src/test/scala/ChiselTests/Outer.scala
+++ b/src/test/scala/ChiselTests/Outer.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Inner extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/Pads.scala b/src/test/scala/ChiselTests/Pads.scala
index a5c03d0b..325d3cc5 100644
--- a/src/test/scala/ChiselTests/Pads.scala
+++ b/src/test/scala/ChiselTests/Pads.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Pads extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/RegisterVecShift.scala b/src/test/scala/ChiselTests/RegisterVecShift.scala
index 2f89ead7..ac2b0d59 100644
--- a/src/test/scala/ChiselTests/RegisterVecShift.scala
+++ b/src/test/scala/ChiselTests/RegisterVecShift.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class RegisterVecShift extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/Risc.scala b/src/test/scala/ChiselTests/Risc.scala
index ec5f1d94..b2a9f65c 100644
--- a/src/test/scala/ChiselTests/Risc.scala
+++ b/src/test/scala/ChiselTests/Risc.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Risc extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/Rom.scala b/src/test/scala/ChiselTests/Rom.scala
index 7c7eb1ac..fb265b61 100644
--- a/src/test/scala/ChiselTests/Rom.scala
+++ b/src/test/scala/ChiselTests/Rom.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Rom extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/SIntOps.scala b/src/test/scala/ChiselTests/SIntOps.scala
index 5fd02c37..6624183c 100644
--- a/src/test/scala/ChiselTests/SIntOps.scala
+++ b/src/test/scala/ChiselTests/SIntOps.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class SIntOps extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/Stack.scala b/src/test/scala/ChiselTests/Stack.scala
index afcbc8bc..c11a9ced 100644
--- a/src/test/scala/ChiselTests/Stack.scala
+++ b/src/test/scala/ChiselTests/Stack.scala
@@ -1,6 +1,7 @@
package ChiselTests
import scala.collection.mutable.{Stack => ScalaStack}
import Chisel._
+import Chisel.testers._
class Stack(val depth: Int) extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/Tbl.scala b/src/test/scala/ChiselTests/Tbl.scala
index 390f5882..c5bc4fe5 100644
--- a/src/test/scala/ChiselTests/Tbl.scala
+++ b/src/test/scala/ChiselTests/Tbl.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class Tbl extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/UIntOps.scala b/src/test/scala/ChiselTests/UIntOps.scala
index 41116029..5215b454 100644
--- a/src/test/scala/ChiselTests/UIntOps.scala
+++ b/src/test/scala/ChiselTests/UIntOps.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class UIntOps extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/VecApp.scala b/src/test/scala/ChiselTests/VecApp.scala
index c32752d6..fef3518d 100644
--- a/src/test/scala/ChiselTests/VecApp.scala
+++ b/src/test/scala/ChiselTests/VecApp.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class VecApp(n: Int, W: Int) extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/VecShiftRegister.scala b/src/test/scala/ChiselTests/VecShiftRegister.scala
index 7a761801..ffcfb7a2 100644
--- a/src/test/scala/ChiselTests/VecShiftRegister.scala
+++ b/src/test/scala/ChiselTests/VecShiftRegister.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class VecShiftRegister extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/VendingMachine.scala b/src/test/scala/ChiselTests/VendingMachine.scala
index 097ee992..7fbfcc62 100644
--- a/src/test/scala/ChiselTests/VendingMachine.scala
+++ b/src/test/scala/ChiselTests/VendingMachine.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
class VendingMachine extends Module {
val io = new Bundle {
diff --git a/src/test/scala/ChiselTests/main.scala b/src/test/scala/ChiselTests/main.scala
index 88ec9218..14745d5a 100644
--- a/src/test/scala/ChiselTests/main.scala
+++ b/src/test/scala/ChiselTests/main.scala
@@ -1,5 +1,6 @@
package ChiselTests
import Chisel._
+import Chisel.testers._
object MiniChisel {
def main(gargs: Array[String]): Unit = {