diff options
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 76796374..65c52015 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -348,7 +348,7 @@ abstract class Data(dirArg: Direction) extends Id { } def toBits(): UInt = { val elts = this.flatten.reverse - Cat(elts.head, elts.tail:_*).asUInt + Cat(elts.head, elts.tail:_*) } def toPort: Port = Port(this, toType) |