diff options
| -rw-r--r-- | core/src/main/scala/chisel3/Aggregate.scala | 5 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 22 |
2 files changed, 25 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index cc5b83d9..82c02cbc 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -226,8 +226,8 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend } // Since all children are the same, we can just use the sample_element rather than all children - // .get is safe because None means mixed directions, we only pass 1 so that's not possible - direction = ActualDirection.fromChildren(Set(sample_element.direction), resolvedDirection).get + direction = + ActualDirection.fromChildren(Set(sample_element.direction), resolvedDirection).getOrElse(ActualDirection.Empty) } // Note: the constructor takes a gen() function instead of a Seq to enforce @@ -321,6 +321,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend case ActualDirection.Bidirectional(ActualDirection.Default) | ActualDirection.Unspecified => SpecifiedDirection.Unspecified case ActualDirection.Bidirectional(ActualDirection.Flipped) => SpecifiedDirection.Flip + case ActualDirection.Empty => SpecifiedDirection.Unspecified } // TODO port technically isn't directly child of this data structure, but the result of some // muxes / demuxes. However, this does make access consistent with the top-level bindings. diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 2eb6ae5f..02743187 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -517,4 +517,26 @@ class VecSpec extends ChiselPropSpec with Utils { property("reduceTree should preserve input/output type") { assertTesterPasses { new ReduceTreeTester() } } + + property("Vecs of empty Bundles and empty Records should work") { + class MyModule(gen: Record) extends Module { + val idx = IO(Input(UInt(2.W))) + val in = IO(Input(gen)) + val out = IO(Output(gen)) + + val reg = RegInit(0.U.asTypeOf(Vec(4, gen))) + reg(idx) := in + out := reg(idx) + } + class EmptyBundle extends Bundle + class EmptyRecord extends Record { + val elements = collection.immutable.ListMap.empty + override def cloneType = (new EmptyRecord).asInstanceOf[this.type] + } + for (gen <- List(new EmptyBundle, new EmptyRecord)) { + val chirrtl = ChiselStage.emitChirrtl(new MyModule(gen)) + chirrtl should include("input in : { }") + chirrtl should include("reg reg : { }[4]") + } + } } |