diff options
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 9584e82a..d9f4ccdb 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -96,9 +96,6 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks dcd shouldBe a [DecoupledIO[UInt]] Queue(dcd) shouldBe a [DecoupledIO[UInt]] Enum(UInt(), 2) shouldBe a [List[UInt]] - val lfsr16 = LFSR16() - lfsr16 shouldBe a [UInt] - lfsr16.getWidth shouldBe (16) ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]] Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt] Mux1H(wire, Seq(wire)) shouldBe a [UInt] @@ -398,4 +395,23 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks elaborate(new Foo) } + behavior of "LFSR16" + + it should "still exist" in { + class Foo extends Module { + val io = IO(new Bundle{}) + + info("Still exists") + val lfsr = LFSR16() + + info("apply method returns a UInt") + lfsr shouldBe a [UInt] + + info("returned UInt has a width of 16") + lfsr.getWidth should be (16) + } + + elaborate(new Foo) + } + } |