diff options
| -rw-r--r-- | core/src/main/scala/chisel3/Aggregate.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/BundleSpec.scala | 34 |
2 files changed, 23 insertions, 13 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index 0031e53b..45ecec36 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -963,6 +963,8 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { for (m <- getPublicFields(classOf[Bundle])) { getBundleField(m) match { case Some(d: Data) => + requireIsChiselType(d) + if (nameMap contains m.getName) { require(nameMap(m.getName) eq d) } else { diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index 5d3f23ec..1d392f5c 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -129,6 +129,27 @@ class BundleSpec extends ChiselFlatSpec with BundleSpecUtils with Utils { }).getMessage should include("aliased fields") } + "Bundles" should "not have bound hardware" in { + (the[ChiselException] thrownBy extractCause[ChiselException] { + ChiselStage.elaborate { new Module { + class MyBundle(val foo: UInt) extends Bundle + val in = IO(Input(new MyBundle(123.U))) // This should error: value passed in instead of type + val out = IO(Output(new MyBundle(UInt(8.W)))) + + out := in + } } + }).getMessage should include("must be a Chisel type, not hardware") + } + "Bundles" should "not recursively contain aggregates with bound hardware" in { + (the[ChiselException] thrownBy extractCause[ChiselException] { + ChiselStage.elaborate { new Module { + class MyBundle(val foo: UInt) extends Bundle + val out = IO(Output(Vec(2, UInt(8.W)))) + val in = IO(Input(new MyBundle(out(0)))) // This should error: Bound aggregate passed + out := in + } } + }).getMessage should include("must be a Chisel type, not hardware") + } "Unbound bundles sharing a field" should "not error" in { ChiselStage.elaborate { new RawModule { @@ -141,17 +162,4 @@ class BundleSpec extends ChiselFlatSpec with BundleSpecUtils with Utils { } } } - - "Bound Data" should "have priority in setting ref over unbound Data" in { - class MyModule extends RawModule { - val foo = IO(new Bundle { - val x = Output(UInt(8.W)) - }) - foo.x := 0.U // getRef on foo.x is None.get without fix - val bar = new Bundle { - val y = foo.x - } - } - ChiselStage.emitChirrtl(new MyModule) - } } |