diff options
| -rw-r--r-- | build.sbt | 7 | ||||
| -rw-r--r-- | main-scala3.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselCli.scala | 2 |
3 files changed, 3 insertions, 8 deletions
@@ -28,7 +28,7 @@ lazy val core = (project in file("core")). buildInfoKeys := Seq[BuildInfoKey](buildInfoPackage, version, scalaVersion, sbtVersion) ). settings( - libraryDependencies += "edu.berkeley.cs" % "firrtl_3" % "1.6-SNAPSHOT", + libraryDependencies += ("edu.berkeley.cs" % "firrtl" % "1.6-SNAPSHOT").cross(CrossVersion.for3Use2_13) ). settings( name := "chisel3-core", @@ -39,11 +39,6 @@ lazy val core = (project in file("core")). "-unchecked", ) ) - .dependsOn(macros) - -lazy val macros = (project in file("macros")) - .settings(name := "chisel-macros") - .settings(commonSettings: _*) // This will always be the root project, even if we are a sub-project. lazy val root = RootProject(file(".")) diff --git a/main-scala3.scala b/main-scala3.scala index f3ff9d4d..dc6b5d84 100644 --- a/main-scala3.scala +++ b/main-scala3.scala @@ -61,5 +61,5 @@ class Tree extends Module { } -@main def runTree(): Unit = println(ChiselStage.emitChirrtl(gen = new Tree)) +@main def runTree(): Unit = println(ChiselStage.emitVerilog(gen = new Tree)) diff --git a/src/main/scala/chisel3/stage/ChiselCli.scala b/src/main/scala/chisel3/stage/ChiselCli.scala index 60e30152..abfd30f2 100644 --- a/src/main/scala/chisel3/stage/ChiselCli.scala +++ b/src/main/scala/chisel3/stage/ChiselCli.scala @@ -4,7 +4,7 @@ package chisel3.stage import firrtl.options.Shell -trait ChiselCli { this: Shell => +trait ChiselCli extends Shell { this: Shell => parser.note("Chisel Front End Options") Seq( NoRunFirrtlCompilerAnnotation, |