Add poison node

4 files changed, 11 insertions, 5 deletions

diff --git a/src/main/scala/Chisel/Builder.scala b/src/main/scala/Chisel/Builder.scala
index 68d996ad..5d003633 100644
--- a/src/main/scala/Chisel/Builder.scala
+++ b/src/main/scala/Chisel/Builder.scala
@@ -88,13 +88,11 @@ private object Builder {
   def components = dynamicContext.components
   def parameterDump = dynamicContext.parameterDump
 
-  def pushCommand(c: Command) {
+  def pushCommand[T <: Command](c: T) = {
     dynamicContext.currentModule.foreach(_._commands += c)
+    c
   }
-  def pushOp[T <: Data](cmd: DefPrim[T]) = {
-    pushCommand(cmd)
-    cmd.id
-  }
+  def pushOp[T <: Data](cmd: DefPrim[T]) = pushCommand(cmd).id
 
   def errors = dynamicContext.errors
   def error(m: => String) = errors.error(m)
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index d8a2c49c..ee322ac5 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -904,3 +904,9 @@ class WhenContext(cond: => Bool)(block: => Unit) {
     res
   }
 }
+
+/** A source of garbage data, used to initialize Wires to a don't-care value. */
+private object Poison extends Command {
+  def apply[T <: Data](t: T): T =
+    pushCommand(DefPoison(t.cloneType)).id
+}
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index 80c6adf0..643135b1 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -8,6 +8,7 @@ private class Emitter(circuit: Circuit) {
   private def emit(e: Command, ctx: Component): String = e match {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_+", "+_)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
+    case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
     case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
     case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
     case e: DefSeqMemory => s"smem ${e.name} : ${e.id.toType}[${e.size}]";
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 209e9f64..35211184 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -145,6 +145,7 @@ case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definiti
 case class DefSeqMemory(id: Data, size: Int) extends Definition
 case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition
 case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
+case class DefPoison[T <: Data](id: T) extends Definition
 case class WhenBegin(pred: Arg) extends Command
 case class WhenElse() extends Command
 case class WhenEnd() extends Command