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authorAndrew Waterman2015-08-17 17:34:21 -0700
committerAndrew Waterman2015-08-17 17:35:35 -0700
commite7baa0a935da93aa1e9e78f7adc1f61222900c60 (patch)
treead7776df0727c66abda55fcebef06c6f60fb4644 /src
parent3dade9a48f059e3eecc7048bcd1cd1db48cdb56a (diff)
Delete unused IR nodes
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Chisel/Emitter.scala2
-rw-r--r--src/main/scala/Chisel/IR.scala2
2 files changed, 0 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index a803c249..c053259d 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -19,8 +19,6 @@ private class Emitter(circuit: Circuit) {
case e: ClockType => s"Clock"
}
private def emit(e: Command, ctx: Component): String = e match {
- case e: DefFlo => s"node ${e.name} = Flo(${e.value})"
- case e: DefDbl => s"node ${e.name} = Dbl(${e.value})"
case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${join(e.args.map(x => x.fullName(ctx)), ", ")})"
case e: DefWire => s"wire ${e.name} : ${emitType(e.kind)}"
case e: DefRegister => s"reg ${e.name} : ${emitType(e.kind)}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index b541e1e2..ad75bea2 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -153,8 +153,6 @@ abstract class Definition extends Command {
def id: HasId
def name = refMap(id).name
}
-case class DefFlo(id: HasId, value: Float) extends Definition
-case class DefDbl(id: HasId, value: Double) extends Definition
case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
case class DefWire(id: HasId, kind: Kind) extends Definition
case class DefRegister(id: HasId, kind: Kind, clock: Arg, reset: Arg) extends Definition