Add explicit types for public methods

7 files changed, 108 insertions, 107 deletions

diff --git a/src/main/scala/Chisel/Builder.scala b/src/main/scala/Chisel/Builder.scala
index 0f085d00..b3c4ae40 100644
--- a/src/main/scala/Chisel/Builder.scala
+++ b/src/main/scala/Chisel/Builder.scala
@@ -83,21 +83,21 @@ private object Builder {
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
   private val currentParamsVar = new DynamicVariable[Parameters](Parameters.empty)
 
-  def dynamicContext = dynamicContextVar.value.get
-  def idGen = dynamicContext.idGen
-  def globalNamespace = dynamicContext.globalNamespace
-  def globalRefMap = dynamicContext.globalRefMap
-  def components = dynamicContext.components
-  def parameterDump = dynamicContext.parameterDump
-
-  def pushCommand[T <: Command](c: T) = {
+  def dynamicContext: DynamicContext = dynamicContextVar.value.get
+  def idGen: IdGen = dynamicContext.idGen
+  def globalNamespace: Namespace = dynamicContext.globalNamespace
+  def globalRefMap: RefMap = dynamicContext.globalRefMap
+  def components: ArrayBuffer[Component] = dynamicContext.components
+  def parameterDump: ParameterDump = dynamicContext.parameterDump
+
+  def pushCommand[T <: Command](c: T): T = {
     dynamicContext.currentModule.foreach(_._commands += c)
     c
   }
-  def pushOp[T <: Data](cmd: DefPrim[T]) = pushCommand(cmd).id
+  def pushOp[T <: Data](cmd: DefPrim[T]): T = pushCommand(cmd).id
 
-  def errors = dynamicContext.errors
-  def error(m: => String) = errors.error(m)
+  def errors: ErrorLog = dynamicContext.errors
+  def error(m: => String): Unit = errors.error(m)
 
   def getParams: Parameters = currentParamsVar.value
   def paramsScope[T](p: Parameters)(body: => T): T = {
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 486f0ff3..6fb0fb25 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -9,18 +9,18 @@ import Builder.dynamicContext
 import PrimOp._
 
 sealed abstract class Direction(name: String) {
-  override def toString = name
+  override def toString: String = name
   def flip: Direction
 }
-object INPUT  extends Direction("input") { def flip = OUTPUT }
-object OUTPUT extends Direction("output") { def flip = INPUT }
-object NO_DIR extends Direction("?") { def flip = NO_DIR }
+object INPUT  extends Direction("input") { override def flip: Direction = OUTPUT }
+object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
+object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
 
 // REVIEW TODO: Should this actually be part of the RTL API? RTL should be
 // considered untouchable from a debugging standpoint?
 object debug {
   // TODO:
-  def apply (arg: Data) = arg
+  def apply (arg: Data): Data = arg
 }
 
 /** This forms the root of the type system for wire data types. The data value
@@ -70,7 +70,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   def isLit(): Boolean = litArg.isDefined
 
   def width: Width
-  final def getWidth = width.get
+  final def getWidth: Int = width.get
 
   // REVIEW TODO: should this actually be part of the Data interface? this is
   // an Aggregate function?
@@ -721,7 +721,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   def ## (other: Bits): UInt = Cat(this, other)
 
   // REVIEW TODO: This just _looks_ wrong.
-  override def toBits = asUInt
+  override def toBits: UInt = asUInt
 
   override def fromBits(n: Bits): this.type = {
     val res = Wire(this).asInstanceOf[this.type]
@@ -814,8 +814,8 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   }
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
-  def unary_- = UInt(0) - this
-  def unary_-% = UInt(0) -% this
+  def unary_- : UInt = UInt(0) - this
+  def unary_-% : UInt = UInt(0) -% this
   def +& (other: UInt): UInt = binop(UInt((this.width max other.width) + 1), AddOp, other)
   def + (other: UInt): UInt = this +% other
   def +% (other: UInt): UInt = binop(UInt(this.width max other.width), AddModOp, other)
@@ -832,9 +832,9 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def ^ (other: UInt): UInt = binop(UInt(this.width max other.width), BitXorOp, other)
 
   // REVIEW TODO: Can this be defined on Bits?
-  def orR = this != UInt(0)
-  def andR = ~this === UInt(0)
-  def xorR = redop(XorReduceOp)
+  def orR: Bool = this != UInt(0)
+  def andR: Bool = ~this === UInt(0)
+  def xorR: Bool = redop(XorReduceOp)
 
   def < (other: UInt): Bool = compop(LessOp, other)
   def > (other: UInt): Bool = compop(GreaterOp, other)
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index ecedb3b7..b4689d61 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -3,7 +3,7 @@
 package Chisel
 
 private class Emitter(circuit: Circuit) {
-  override def toString = res.toString
+  override def toString: String = res.toString
 
   private def emitPort(e: Port): String =
     s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
diff --git a/src/main/scala/Chisel/Error.scala b/src/main/scala/Chisel/Error.scala
index d9e6db6f..30f6b527 100644
--- a/src/main/scala/Chisel/Error.scala
+++ b/src/main/scala/Chisel/Error.scala
@@ -6,13 +6,13 @@ import scala.collection.mutable.ArrayBuffer
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
 private object throwException {
-  def apply(s: String, t: Throwable = null) =
+  def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
 private class ErrorLog {
-  def hasErrors = errors.exists(_.isFatal)
+  def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
   def error(m: => String): Unit =
@@ -75,14 +75,14 @@ private abstract class LogEntry(msg: => String, line: Option[StackTraceElement])
 }
 
 private class Error(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
-  override def isFatal = true
-  def format = tag("error", Console.RED)
+  override def isFatal: Boolean = true
+  def format: String = tag("error", Console.RED)
 }
 
 private class Warning(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
-  def format = tag("warn", Console.YELLOW)
+  def format: String = tag("warn", Console.YELLOW)
 }
 
 private class Info(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
-  def format = tag("info", Console.MAGENTA)
+  def format: String = tag("info", Console.MAGENTA)
 }
diff --git a/src/main/scala/Chisel/FP.scala b/src/main/scala/Chisel/FP.scala
index f997ac8f..bad62e00 100644
--- a/src/main/scala/Chisel/FP.scala
+++ b/src/main/scala/Chisel/FP.scala
@@ -7,11 +7,11 @@ import Builder.pushOp
 /// FLO
 
 case class FloLit(num: Float) extends Arg {
-  def name = s"Flo(${num.toString})"
+  def name: String = s"Flo(${num.toString})"
 }
 
 case class DblLit(num: Double) extends Arg {
-  def name = s"Dbl(${num.toString})"
+  def name: String = s"Dbl(${num.toString})"
 }
 
 object Flo {
@@ -60,7 +60,7 @@ sealed abstract class FloBase[T <: Data](dir: Direction, width: Width) extends E
   protected def compop(op: PrimOp, other: T): Bool =
     pushOp(DefPrim(Bool(), op, this.ref, other.ref))
 
-  def toUInt = toBits
+  def toUInt: UInt = toBits
 }
 
 class Flo(dir: Direction = NO_DIR, val value:Option[FloLit] = None)
@@ -78,30 +78,30 @@ class Flo(dir: Direction = NO_DIR, val value:Option[FloLit] = None)
   def fromInt(x: Int): Flo =
     Flo(x.toFloat).asInstanceOf[this.type]
 
-  def unary_-() = unop(FloNeg)
-  def +  (b: Flo) = binop(FloAdd, b)
-  def -  (b: Flo) = binop(FloSub, b)
-  def *  (b: Flo) = binop(FloMul, b)
-  def /  (b: Flo) = binop(FloDiv, b)
-  def %  (b: Flo) = binop(FloMod, b)
-  def ===(b: Flo) = compop(FloEqual, b)
-  def != (b: Flo) = compop(FloNotEqual, b)
-  def >  (b: Flo) = compop(FloGreater, b)
-  def <  (b: Flo) = compop(FloLess, b)
-  def <= (b: Flo) = compop(FloLessEqual, b)
-  def >= (b: Flo) = compop(FloGreaterEqual, b)
-  def pow (b: Flo) = binop(FloPow, b)
-  def sin = unop(FloSin)
-  def cos = unop(FloCos)
-  def tan = unop(FloTan)
-  def asin = unop(FloAsin)
-  def acos = unop(FloAcos)
-  def atan = unop(FloAtan)
-  def sqrt = unop(FloSqrt)
-  def floor = unop(FloFloor)
-  def ceil = unop(FloCeil)
-  def round = unop(FloRound)
-  def log = unop(FloLog)
+  def unary_-(): Flo = unop(FloNeg)
+  def +  (b: Flo): Flo = binop(FloAdd, b)
+  def -  (b: Flo): Flo = binop(FloSub, b)
+  def *  (b: Flo): Flo = binop(FloMul, b)
+  def /  (b: Flo): Flo = binop(FloDiv, b)
+  def %  (b: Flo): Flo = binop(FloMod, b)
+  def ===(b: Flo): Bool = compop(FloEqual, b)
+  def != (b: Flo): Bool = compop(FloNotEqual, b)
+  def >  (b: Flo): Bool = compop(FloGreater, b)
+  def <  (b: Flo): Bool = compop(FloLess, b)
+  def <= (b: Flo): Bool = compop(FloLessEqual, b)
+  def >= (b: Flo): Bool = compop(FloGreaterEqual, b)
+  def pow (b: Flo): Flo = binop(FloPow, b)
+  def sin: Flo = unop(FloSin)
+  def cos: Flo = unop(FloCos)
+  def tan: Flo = unop(FloTan)
+  def asin: Flo = unop(FloAsin)
+  def acos: Flo = unop(FloAcos)
+  def atan: Flo = unop(FloAtan)
+  def sqrt: Flo = unop(FloSqrt)
+  def floor: Flo = unop(FloFloor)
+  def ceil: Flo = unop(FloCeil)
+  def round: Flo = unop(FloRound)
+  def log: Flo = unop(FloLog)
 }
 
 /// DBL
@@ -160,30 +160,30 @@ class Dbl(dir: Direction, val value: Option[DblLit] = None) extends FloBase[Dbl]
   def fromInt(x: Int): this.type =
     Dbl(x.toDouble).asInstanceOf[this.type]
 
-  def unary_-() = unop(DblNeg)
-  def +  (b: Dbl) = binop(DblAdd, b)
-  def -  (b: Dbl) = binop(DblSub, b)
-  def *  (b: Dbl) = binop(DblMul, b)
-  def /  (b: Dbl) = binop(DblDiv, b)
-  def %  (b: Dbl) = binop(DblMod, b)
-  def ===(b: Dbl) = compop(DblEqual, b)
-  def != (b: Dbl) = compop(DblNotEqual, b)
-  def >  (b: Dbl) = compop(DblGreater, b)
-  def <  (b: Dbl) = compop(DblLess, b)
-  def <= (b: Dbl) = compop(DblLessEqual, b)
-  def >= (b: Dbl) = compop(DblGreaterEqual, b)
-  def pow (b: Dbl) = binop(DblPow, b)
-  def sin = unop(DblSin)
-  def cos = unop(DblCos)
-  def tan = unop(DblTan)
-  def asin = unop(DblAsin)
-  def acos = unop(DblAcos)
-  def atan = unop(DblAtan)
-  def sqrt = unop(DblSqrt)
-  def floor = unop(DblFloor)
-  def ceil = unop(DblCeil)
-  def round = unop(DblRound)
-  def log = unop(DblLog)
+  def unary_-(): Dbl = unop(DblNeg)
+  def +  (b: Dbl): Dbl = binop(DblAdd, b)
+  def -  (b: Dbl): Dbl = binop(DblSub, b)
+  def *  (b: Dbl): Dbl = binop(DblMul, b)
+  def /  (b: Dbl): Dbl = binop(DblDiv, b)
+  def %  (b: Dbl): Dbl = binop(DblMod, b)
+  def ===(b: Dbl): Bool = compop(DblEqual, b)
+  def != (b: Dbl): Bool = compop(DblNotEqual, b)
+  def >  (b: Dbl): Bool = compop(DblGreater, b)
+  def <  (b: Dbl): Bool = compop(DblLess, b)
+  def <= (b: Dbl): Bool = compop(DblLessEqual, b)
+  def >= (b: Dbl): Bool = compop(DblGreaterEqual, b)
+  def pow (b: Dbl): Dbl = binop(DblPow, b)
+  def sin: Dbl = unop(DblSin)
+  def cos: Dbl = unop(DblCos)
+  def tan: Dbl = unop(DblTan)
+  def asin: Dbl = unop(DblAsin)
+  def acos: Dbl = unop(DblAcos)
+  def atan: Dbl = unop(DblAtan)
+  def sqrt: Dbl = unop(DblSqrt)
+  def floor: Dbl = unop(DblFloor)
+  def ceil: Dbl = unop(DblCeil)
+  def round: Dbl = unop(DblRound)
+  def log: Dbl = unop(DblLog)
 }
 
 object Sin {
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 78c08c7e..d49d260d 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -3,7 +3,7 @@
 package Chisel
 
 case class PrimOp(val name: String) {
-  override def toString = name
+  override def toString: String = name
 }
 
 object PrimOp {
@@ -46,8 +46,8 @@ abstract class Arg {
 }
 
 case class Node(id: HasId) extends Arg {
-  override def fullName(ctx: Component) = id.getRef.fullName(ctx)
-  def name = id.getRef.name
+  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
+  def name: String = id.getRef.name
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
@@ -61,36 +61,37 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
 }
 
 case class ILit(n: BigInt) extends Arg {
-  def name = n.toString
+  def name: String = n.toString
 }
 
 case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
-  def name = "UInt<" + width + ">(\"h0" + num.toString(16) + "\")"
-  def minWidth = 1 max n.bitLength
+  def name: String = "UInt<" + width + ">(\"h0" + num.toString(16) + "\")"
+  def minWidth: Int = 1 max n.bitLength
 
   require(n >= 0, s"UInt literal ${n} is negative")
 }
 
 case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
-  def name = {
+  def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asSInt(${ULit(unsigned, width).name})"
   }
-  def minWidth = 1 + n.bitLength
+  def minWidth: Int = 1 + n.bitLength
 }
 
 case class Ref(name: String) extends Arg
 case class ModuleIO(mod: Module, name: String) extends Arg {
-  override def fullName(ctx: Component) =
+  override def fullName(ctx: Component): String =
     if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
 }
 case class Slot(imm: Node, name: String) extends Arg {
-  override def fullName(ctx: Component) =
-    if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}"
+  override def fullName(ctx: Component): String =
+    if (imm.fullName(ctx).isEmpty) name
+    else s"${imm.fullName(ctx)}.${name}"
 }
 case class Index(imm: Arg, value: Int) extends Arg {
-  def name = s"[$value]"
-  override def fullName(ctx: Component) = s"${imm.fullName(ctx)}[$value]"
+  def name: String = s"[$value]"
+  override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[$value]"
 }
 
 object Width {
@@ -113,27 +114,27 @@ sealed abstract class Width {
 }
 
 sealed case class UnknownWidth() extends Width {
-  def known = false
-  def get = None.get
-  def op(that: Width, f: (W, W) => W) = this
-  override def toString = "?"
+  def known: Boolean = false
+  def get: Int = None.get
+  def op(that: Width, f: (W, W) => W): Width = this
+  override def toString: String = "?"
 }
 
 sealed case class KnownWidth(value: Int) extends Width {
   require(value >= 0)
-  def known = true
-  def get = value
-  def op(that: Width, f: (W, W) => W) = that match {
+  def known: Boolean = true
+  def get: Int = value
+  def op(that: Width, f: (W, W) => W): Width = that match {
     case KnownWidth(x) => KnownWidth(f(value, x))
     case _ => that
   }
-  override def toString = value.toString
+  override def toString: String = value.toString
 }
 
 abstract class Command
 abstract class Definition extends Command {
   def id: HasId
-  def name = id.getRef.name
+  def name: String = id.getRef.name
 }
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefWire(id: Data) extends Definition
@@ -153,5 +154,5 @@ case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[C
 case class Port(id: Data, dir: Direction)
 
 case class Circuit(name: String, components: Seq[Component], refMap: RefMap, parameterDump: ParameterDump) {
-  def emit = new Emitter(this).toString
+  def emit: String = new Emitter(this).toString
 }
diff --git a/src/main/scala/Chisel/Utils.scala b/src/main/scala/Chisel/Utils.scala
index a7a18193..68005f7f 100644
--- a/src/main/scala/Chisel/Utils.scala
+++ b/src/main/scala/Chisel/Utils.scala
@@ -89,12 +89,12 @@ object RegInit {
 /** A register with an Enable signal */
 object RegEnable
 {
-  def apply[T <: Data](updateData: T, enable: Bool) = {
+  def apply[T <: Data](updateData: T, enable: Bool): T = {
     val r = Reg(updateData)
     when (enable) { r := updateData }
     r
   }
-  def apply[T <: Data](updateData: T, resetData: T, enable: Bool) = {
+  def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
     val r = RegInit(resetData)
     when (enable) { r := updateData }
     r
@@ -185,7 +185,7 @@ object is { // Begin deprecation of non-type-parameterized is statements.
   * } }}}*/
 object switch {
   def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl
-  def impl(c: Context)(cond: c.Tree)(x: c.Tree) = { import c.universe._
+  def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val sc = c.universe.internal.reificationSupport.freshTermName("sc")
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
       case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")